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[209.132.180.67]) by mx.google.com with ESMTP id zk5si21621640pac.234.2016.02.01.07.08.40; Mon, 01 Feb 2016 07:08:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933203AbcBAPIa (ORCPT + 30 others); Mon, 1 Feb 2016 10:08:30 -0500 Received: from mail-wm0-f42.google.com ([74.125.82.42]:36537 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933124AbcBAPI0 (ORCPT ); Mon, 1 Feb 2016 10:08:26 -0500 Received: by mail-wm0-f42.google.com with SMTP id p63so75029299wmp.1 for ; Mon, 01 Feb 2016 07:08:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+dkwRU5OtpTp+RwMJ2WdMrtGcToTA+Cqv892ol80y3w=; b=VT75GTqsew5q/rnlrPODZF+aI5pg4rkWzj1hYIGVvamDRZaobGhqMMeu0DhexiYIr4 dS7O4Kc6mw+b6LJZTHBMPOCF2cbxXQyIKpxL5ZkHTxZBG1vtAeAb9Z5r53OEYUxvYCOW sDsvtF51da8djfD7TozoVmGc06MsXAY4+yYXE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+dkwRU5OtpTp+RwMJ2WdMrtGcToTA+Cqv892ol80y3w=; b=XIOjrvcQmXNr9VmJHf5Ii8uq2BoJHszXSgDpsC2MtuY8A9ysh/JoPa6BdaP+Fl9FCM PghOoqATPgmIlbWgR6JXQ37ETKR8Z1MvSA1+SHLN/bPgW6v5TNyKKF1wuNOXI9tgPHur EhbpZiItLNMQHDMCUI4a/HYIDl0ZKeHGm0bcjKU/mZjbwoQ01aXnMYM80rs1ZgPettW8 6LtZJhh90JWgUxZkhMjP+1UHQYXuY7HQBPA2aPMzO29xlpkrTd/zaGSuioY26PvWjnHk pUdHBbuuKtd0JfpgrBvoe9/kcbdXKlR0FV4HSkTgy4nyBK+hPAkcss2hZAaFjG4Ma6W4 x+Dg== X-Gm-Message-State: AG10YOQS7bA7EvunORFe4iJ/yLLA488l7cCVVMZVRbXdfW9HxFoKAyGM6UXwA2eDzlzchque X-Received: by 10.194.104.6 with SMTP id ga6mr23115967wjb.17.1454339305629; Mon, 01 Feb 2016 07:08:25 -0800 (PST) Received: from mms.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.googlemail.com with ESMTPSA id qs1sm29444930wjc.2.2016.02.01.07.08.23 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 01 Feb 2016 07:08:24 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v5 3/3] clk: qcom: Add A53 clock driver Date: Mon, 1 Feb 2016 17:07:51 +0200 Message-Id: <1454339271-643-4-git-send-email-georgi.djakov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1454339271-643-1-git-send-email-georgi.djakov@linaro.org> References: <1454339271-643-1-git-send-email-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a driver for the A53 Clock Controller. It is a hardware block that implements a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated A53 PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on platforms such as MSM8916. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/clock/qcom,a53cc.txt | 22 +++ drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a53cc.c | 162 ++++++++++++++++++++ 4 files changed, 193 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53cc.txt create mode 100644 drivers/clk/qcom/a53cc.c diff --git a/Documentation/devicetree/bindings/clock/qcom,a53cc.txt b/Documentation/devicetree/bindings/clock/qcom,a53cc.txt new file mode 100644 index 000000000000..a025f062f177 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a53cc.txt @@ -0,0 +1,22 @@ +Qualcomm A53 CPU Clock Controller Binding +------------------------------------------------ +The A53 CPU Clock Controller is hardware, which provides a combined +mux and divider functionality for the CPU clocks. It can choose between +a fixed rate clock and the dedicated A53 PLL. + +Required properties : +- compatible : shall contain: + + "qcom,a53cc" + +- reg : shall contain base register location and length + of the APCS region +- #clock-cells : shall contain 1 + +Example: + + apcs: syscon@b011000 { + compatible = "qcom,a53cc", "syscon"; + reg = <0x0b011000 0x1000>; + #clock-cells = <1>; + }; diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d06cf687be4f..27a1622ca891 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -132,3 +132,11 @@ config QCOM_A53PLL support for CPU frequencies above 1GHz. Say Y if you want to support CPU frequency scaling on devices such as MSM8916. + +config QCOM_A53CC + bool "A53 Clock Controller" + depends on COMMON_CLK_QCOM && QCOM_A53PLL + help + Support for the A53 clock controller on some Qualcomm devices. + Say Y if you want to support CPU frequency scaling on devices + such as MSM8916. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index bc7637516a6e..9a67697b9540 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -26,4 +26,5 @@ obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_QCOM_A53CC) += a53cc.o obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o diff --git a/drivers/clk/qcom/a53cc.c b/drivers/clk/qcom/a53cc.c new file mode 100644 index 000000000000..74b462893045 --- /dev/null +++ b/drivers/clk/qcom/a53cc.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2016, Linaro Limited. All rights reserved. + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include "clk-regmap.h" +#include "clk-regmap-mux-div.h" + +enum { + P_GPLL0, + P_A53PLL, +}; + +static const struct parent_map gpll0_a53cc_map[] = { + { P_GPLL0, 4 }, + { P_A53PLL, 5 }, +}; + +static const char * const gpll0_a53cc[] = { + "gpll0_vote", + "a53pll", +}; + +static const struct regmap_config a53cc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, + .fast_io = true, + .val_format_endian = REGMAP_ENDIAN_LITTLE, +}; + +static const struct of_device_id qcom_a53cc_match_table[] = { + { .compatible = "qcom,a53cc" }, + { } +}; + +/* + * We use the notifier function for switching to a temporary safe configuration + * (mux and divider), while the a53 pll is reconfigured. + */ +static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data) +{ + int ret = 0; + struct clk_regmap_mux_div *md = container_of(nb, + struct clk_regmap_mux_div, + clk_nb); + + if (event == PRE_RATE_CHANGE) + ret = __mux_div_set_src_div(md, md->safe_src, md->safe_div); + + return notifier_from_errno(ret); +} + +static int qcom_a53cc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk_regmap_mux_div *a53cc; + struct resource *res; + void __iomem *base; + struct clk *clk, *pclk; + struct regmap *regmap; + struct clk_init_data init; + int ret; + + a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL); + if (!a53cc) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + a53cc->reg_offset = 0x50, + a53cc->hid_width = 5, + a53cc->hid_shift = 0, + a53cc->src_width = 3, + a53cc->src_shift = 8, + a53cc->safe_src = 4, + a53cc->safe_div = 3, + a53cc->parent_map = gpll0_a53cc_map, + + init.name = "a53mux", + init.parent_names = gpll0_a53cc, + init.num_parents = 2, + init.ops = &clk_regmap_mux_div_ops, + init.flags = CLK_SET_RATE_PARENT; + a53cc->clkr.hw.init = &init; + + pclk = __clk_lookup(gpll0_a53cc[1]); + if (!pclk) + return -EPROBE_DEFER; + + /* activate A53 PLL output */ + ret = clk_prepare_enable(pclk); + if (ret) { + dev_err(dev, "failed to enable %s: %d\n", gpll0_a53cc[1], ret); + return ret; + } + + a53cc->clk_nb.notifier_call = a53cc_notifier_cb; + ret = clk_notifier_register(pclk, &a53cc->clk_nb); + if (ret) { + dev_err(dev, "failed to register clock notifier: %d\n", ret); + return ret; + } + + regmap = devm_regmap_init_mmio(dev, base, &a53cc_regmap_config); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(dev, "failed to init regmap mmio: %d\n", ret); + goto err; + } + + a53cc->clkr.regmap = regmap; + + clk = devm_clk_register_regmap(dev, &a53cc->clkr); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err(dev, "failed to register regmap clock: %d\n", ret); + goto err; + } + + ret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get, clk); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + goto err; + } + + return 0; +err: + clk_notifier_unregister(pclk, &a53cc->clk_nb); + return ret; +} + +static struct platform_driver qcom_a53cc_driver = { + .probe = qcom_a53cc_probe, + .driver = { + .name = "qcom-a53cc", + .of_match_table = qcom_a53cc_match_table, + }, +}; + +builtin_platform_driver(qcom_a53cc_driver);