From patchwork Tue Jan 26 22:46:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 105017 Delivered-To: patch@linaro.org Received: by 10.112.130.2 with SMTP id oa2csp2249187lbb; Tue, 26 Jan 2016 14:47:05 -0800 (PST) X-Received: by 10.98.68.73 with SMTP id r70mr37766129pfa.12.1453848425195; Tue, 26 Jan 2016 14:47:05 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id vt4si4734366pab.8.2016.01.26.14.47.04; Tue, 26 Jan 2016 14:47:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753212AbcAZWrD (ORCPT + 30 others); Tue, 26 Jan 2016 17:47:03 -0500 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:47668 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752791AbcAZWrA (ORCPT ); Tue, 26 Jan 2016 17:47:00 -0500 Received: from cpc11-sgyl31-2-0-cust672.sgyl.cable.virginm.net ([94.175.94.161] helo=debutante) by mezzanine.sirena.org.uk with esmtpsa (TLS1.2:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1aOCNy-0004Jz-Bj; Tue, 26 Jan 2016 22:46:55 +0000 Received: from broonie by debutante with local (Exim 4.86) (envelope-from ) id 1aOCNv-0006V6-F9; Tue, 26 Jan 2016 22:46:51 +0000 From: Mark Brown To: Ralf Baechle , Kevin Cernekee Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Johannes Berg , Simon Arlott , Arnd Bergmann , Mark Brown Date: Tue, 26 Jan 2016 22:46:49 +0000 Message-Id: <1453848410-24949-1-git-send-email-broonie@kernel.org> X-Mailer: git-send-email 2.7.0.rc3 X-SA-Exim-Connect-IP: 94.175.94.161 X-SA-Exim-Mail-From: broonie@sirena.org.uk X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on mezzanine.sirena.org.uk X-Spam-Level: X-Spam-Status: No, score=-2.9 required=5.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.3.2 Subject: [PATCH 1/2] regmap: Add explict native endian flag to DT bindings X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently the binding document says that if no endianness is configured we use native endian but this is not in fact true for all binding types and we do have some devices that really want native endianness such as Broadcom MIPS SoCs where switching the endianness of the CPU also switches the endianness of external IPs. Provide an explicit option for this. Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regmap/regmap.txt | 11 +++++++---- drivers/base/regmap/regmap.c | 2 ++ 2 files changed, 9 insertions(+), 4 deletions(-) -- 2.7.0.rc3 diff --git a/Documentation/devicetree/bindings/regmap/regmap.txt b/Documentation/devicetree/bindings/regmap/regmap.txt index b494f8b8ef72..e98a9652ccc8 100644 --- a/Documentation/devicetree/bindings/regmap/regmap.txt +++ b/Documentation/devicetree/bindings/regmap/regmap.txt @@ -5,15 +5,18 @@ Index Device Endianness properties --------------------------------------------------- 1 BE 'big-endian' 2 LE 'little-endian' +3 Native 'native-endian' For one device driver, which will run in different scenarios above on different SoCs using the devicetree, we need one way to simplify this. -Required properties: -- {big,little}-endian: these are boolean properties, if absent - meaning that the CPU and the Device are in the same endianness mode, - these properties are for register values and all the buffers only. +Optional properties: +- {big,little,native}-endian: these are boolean properties, if absent + then the implementation will choose a default based on the device + being controlled. These properties are for register values and all + the buffers only. Native endian means that the CPU and device have + the same endianness. Examples: Scenario 1 : CPU in LE mode & device in LE mode. diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index 4ac63c0e50c7..57a7d144e629 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -500,6 +500,8 @@ enum regmap_endian regmap_get_val_endian(struct device *dev, endian = REGMAP_ENDIAN_BIG; else if (of_property_read_bool(np, "little-endian")) endian = REGMAP_ENDIAN_LITTLE; + else if (of_property_read_bool(np, "native-endian")) + endian = REGMAP_ENDIAN_NATIVE; /* If the endianness was specified in DT, use that */ if (endian != REGMAP_ENDIAN_DEFAULT)