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[209.132.180.67]) by mx.google.com with ESMTP id x14si4670861pfi.39.2016.01.12.23.08.32; Tue, 12 Jan 2016 23:08:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@cavium-com.20150623.gappssmtp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755254AbcAMHIa (ORCPT + 29 others); Wed, 13 Jan 2016 02:08:30 -0500 Received: from mail-ig0-f178.google.com ([209.85.213.178]:33577 "EHLO mail-ig0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755104AbcAMHIZ (ORCPT ); Wed, 13 Jan 2016 02:08:25 -0500 Received: by mail-ig0-f178.google.com with SMTP id z14so161733692igp.0 for ; Tue, 12 Jan 2016 23:08:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cavium-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fhdNYCNg1pXV7xWSl9UltK1jlijyrEzfSQTRWjzvDUY=; b=HVNHBnIz0YNYD5z37+iL56wlNXGsuxpz5NgXhyz9MMprGNUHiM+/afoe+Mw7pP1t0y Ey7tVN3t+XaMKHQ5nqJcUAnpKeydiYfpehDfCizvTQRAaEqrSsTKIt47c9TaAAyyWW2V 50umrGuzsrkJqFib6zElPF7S4xaeNay5V8RacICwXAhjIr3JEYNDrB5BraPa0gYM/qKM cClTtDlztUF3u5bVEA3+5WyPnzbRVvNtPf0dWP6aNyjAbMRuYLozdG/DtXs9rvTK2+jH w3kkog7QFps4KQ7bFf3fj8gsYkIbImK1BlhiyFO+qpxzPRNva5SK10lctDJux41QT9gW +ptw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fhdNYCNg1pXV7xWSl9UltK1jlijyrEzfSQTRWjzvDUY=; b=Vzn7TIEWnGNL8oQ/QJ8FqJLFDaeRv/MHD+tVrdLZmLYGKk9k+gQE0yd+LP4XQn1WcL 77qKD622pKSphAkMjG//I4kdAJEPgm68RR/dn6j9GzwsNeFRQJOktAtUikfWtIBRDUTc hIeGWCezVy+ZNgkv51wEPVQwHzHkolu2573II5bVXUB3Fm/jJU75eOIiBcTca3awY/ha OY6cUAVRLIkRVKGWykLQdccwJXhNBfesXzitfH1AbcmftGC1ApOgV56qf2FDX9+bn0j8 w3SYdGhwhyMFg90xhV57RqUscf9vtJbrY/i1gbsaSAV0ydQixTnf3b7CNZs/2N2iyIPq E1yA== X-Gm-Message-State: ALoCoQnz8th5fwNxnHcmiHBsnLWFUNudCcVK2GnRweG9KtmbNrZ6ZrOt8YgCGYZOd8cAOEsj/GkkbhvwnqljZsCG2kZFjl5NaQ== X-Received: by 10.50.150.100 with SMTP id uh4mr21008597igb.45.1452668905015; Tue, 12 Jan 2016 23:08:25 -0800 (PST) Received: from localhost.localdomain ([64.2.3.194]) by smtp.gmail.com with ESMTPSA id m6sm7611533ige.3.2016.01.12.23.08.24 (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 12 Jan 2016 23:08:24 -0800 (PST) Received: from localhost.localdomain (apinskidesktop [127.0.0.1]) by localhost.localdomain (8.14.3/8.14.3/Debian-9.4) with ESMTP id u0D78NDa003610 (version=TLSv1/SSLv3 cipher=DHE-DSS-AES256-SHA bits=256 verify=NO); Tue, 12 Jan 2016 23:08:23 -0800 Received: (from apinski@localhost) by localhost.localdomain (8.14.3/8.14.3/Submit) id u0D78NIB003609; Tue, 12 Jan 2016 23:08:23 -0800 From: Andrew Pinski To: pinskia@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Will Deacon Cc: Andrew Pinski Subject: [PATCH 1/5] ARM64: Support midr detected cpufeature Date: Tue, 12 Jan 2016 23:08:15 -0800 Message-Id: <1452668899-3553-2-git-send-email-apinski@cavium.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1452668899-3553-1-git-send-email-apinski@cavium.com> References: <1452668899-3553-1-git-send-email-apinski@cavium.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A soon to be added feature is marking the need for software prefetching of 128 byte cache line. This feature is not detected via bits of a system register but rather matching of the Machine ID register. This adds support for detecting a cpufeature by the MIDR. Signed-off-by: Andrew Pinski --- arch/arm64/include/asm/cpufeature.h | 26 ++++++++++++++++++++++++-- arch/arm64/include/asm/cputype.h | 7 +++++++ arch/arm64/kernel/cpu_errata.c | 26 -------------------------- arch/arm64/kernel/cpufeature.c | 21 ++++++++++++++++++++- 4 files changed, 51 insertions(+), 29 deletions(-) -- 1.7.2.5 diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 8136afc..92aaac6 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -11,6 +11,7 @@ #include #include +#include /* * In the arm64 world (as in the ARM world), elf_hwcap is used both internally @@ -78,14 +79,14 @@ struct arm64_cpu_capabilities { u16 capability; bool (*matches)(const struct arm64_cpu_capabilities *); void (*enable)(void *); /* Called on all active CPUs */ + u32 sys_reg; union { - struct { /* To be used for erratum handling only */ + struct { /* MIDR matching used if sys_reg is SYS_MIDR_EL1. */ u32 midr_model; u32 midr_range_min, midr_range_max; }; struct { /* Feature register checking */ - u32 sys_reg; int field_pos; int min_field_value; int hwcap_type; @@ -94,6 +95,27 @@ struct arm64_cpu_capabilities { }; }; +static bool __maybe_unused +is_affected_midr_range(const struct arm64_cpu_capabilities *entry) +{ + u32 midr = read_cpuid_id(); + + if ((midr & CPU_MODEL_MASK) != entry->midr_model) + return false; + + midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; + + return (midr >= entry->midr_range_min && midr <= entry->midr_range_max); +} + +#define MIDR_RANGE(model, min, max) \ + .matches = is_affected_midr_range, \ + .sys_reg = SYS_MIDR_EL1, \ + .midr_model = model, \ + .midr_range_min = min, \ + .midr_range_max = max + + extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); static inline bool cpu_have_feature(unsigned int num) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 1a59493..cd99d28a 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -75,6 +75,13 @@ #define CAVIUM_CPU_PART_THUNDERX 0x0A1 +#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) +#define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) +#define MIDR_THUNDERX MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + +#define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ + MIDR_ARCHITECTURE_MASK) + #ifndef __ASSEMBLY__ /* diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 01248e8..cec63a9 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -21,32 +21,6 @@ #include #include -#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) -#define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) -#define MIDR_THUNDERX MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) - -#define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ - MIDR_ARCHITECTURE_MASK) - -static bool __maybe_unused -is_affected_midr_range(const struct arm64_cpu_capabilities *entry) -{ - u32 midr = read_cpuid_id(); - - if ((midr & CPU_MODEL_MASK) != entry->midr_model) - return false; - - midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; - - return (midr >= entry->midr_range_min && midr <= entry->midr_range_max); -} - -#define MIDR_RANGE(model, min, max) \ - .matches = is_affected_midr_range, \ - .midr_model = model, \ - .midr_range_min = min, \ - .midr_range_max = max - const struct arm64_cpu_capabilities arm64_errata[] = { #if defined(CONFIG_ARM64_ERRATUM_826319) || \ defined(CONFIG_ARM64_ERRATUM_827319) || \ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 0669c63..b0ee60e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -869,8 +869,27 @@ void verify_local_cpu_capabilities(void) caps = arm64_features; for (i = 0; caps[i].desc; i++) { - if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg) + /* + * If the feature is not enable already, then don't try to + * enable. + */ + if (!cpus_have_cap(caps[i].capability)) + continue; + if (!caps[i].sys_reg) + continue; + /* Handle MIDR matching seperately. */ + if (caps[i].sys_reg == SYS_MIDR_EL1) { + /* + * If the new CPU is a different MIDR it means the + * feature is missing, we cannot proceed further, + * park the cpu. + */ + if (!is_affected_midr_range (&caps[i])) + fail_incapable_cpu("arm64_features", &caps[i]); + if (caps[i].enable) + caps[i].enable(NULL); continue; + } /* * If the new CPU misses an advertised feature, we cannot proceed * further, park the cpu.