From patchwork Thu Nov 19 23:05:07 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Mason X-Patchwork-Id: 57053 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp136187lbb; Thu, 19 Nov 2015 15:06:01 -0800 (PST) X-Received: by 10.68.143.40 with SMTP id sb8mr8254593pbb.29.1447974361727; Thu, 19 Nov 2015 15:06:01 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ti10si14595491pab.52.2015.11.19.15.06.01; Thu, 19 Nov 2015 15:06:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161505AbbKSXF7 (ORCPT + 28 others); Thu, 19 Nov 2015 18:05:59 -0500 Received: from mail-gw3-out.broadcom.com ([216.31.210.64]:9438 "EHLO mail-gw3-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934059AbbKSXF4 (ORCPT ); Thu, 19 Nov 2015 18:05:56 -0500 X-IronPort-AV: E=Sophos;i="5.20,319,1444719600"; d="scan'208";a="80891513" Received: from irvexchcas08.broadcom.com (HELO IRVEXCHCAS08.corp.ad.broadcom.com) ([10.9.208.57]) by mail-gw3-out.broadcom.com with ESMTP; 19 Nov 2015 15:37:24 -0800 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.3.235.1; Thu, 19 Nov 2015 15:05:55 -0800 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.3.235.1; Thu, 19 Nov 2015 15:05:54 -0800 Received: from venom.rtp.broadcom.com (unknown [10.27.64.103]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 2C32D41023; Thu, 19 Nov 2015 15:01:57 -0800 (PST) From: Jon Mason To: Florian Fainelli , Hauke Mehrtens , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , "Russell King" CC: , , , Subject: [PATCH v2 1/3] ARM: dts: enable clock support for BCM5301X Date: Thu, 19 Nov 2015 18:05:07 -0500 Message-ID: <1447974309-29566-2-git-send-email-jonmason@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1447974309-29566-1-git-send-email-jonmason@broadcom.com> References: <1447974309-29566-1-git-send-email-jonmason@broadcom.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Replace current device tree dummy clocks with real clock support for Broadcom Northstar SoCs. Signed-off-by: Jon Mason --- arch/arm/boot/dts/bcm5301x.dtsi | 92 +++++++++++++++++++++++++++++++---------- 1 file changed, 71 insertions(+), 21 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 6f50f67..65a1309 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -8,6 +8,7 @@ * Licensed under the GNU/GPL. See COPYING for details. */ +#include #include #include #include @@ -27,7 +28,7 @@ compatible = "ns16550"; reg = <0x0300 0x100>; interrupts = ; - clock-frequency = <100000000>; + clocks = <&iprocslow>; status = "disabled"; }; @@ -35,48 +36,55 @@ compatible = "ns16550"; reg = <0x0400 0x100>; interrupts = ; - clock-frequency = <100000000>; + clocks = <&iprocslow>; status = "disabled"; }; }; mpcore { compatible = "simple-bus"; - ranges = <0x00000000 0x19020000 0x00003000>; + ranges = <0x00000000 0x19000000 0x00023000>; #address-cells = <1>; #size-cells = <1>; - scu@0000 { + a9pll: arm_clk@00000 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x00000 0x1000>; + }; + + scu@20000 { compatible = "arm,cortex-a9-scu"; - reg = <0x0000 0x100>; + reg = <0x20000 0x100>; }; - timer@0200 { + timer@20200 { compatible = "arm,cortex-a9-global-timer"; - reg = <0x0200 0x100>; + reg = <0x20200 0x100>; interrupts = ; - clocks = <&clk_periph>; + clocks = <&periph_clk>; }; - local-timer@0600 { + local-timer@20600 { compatible = "arm,cortex-a9-twd-timer"; - reg = <0x0600 0x100>; + reg = <0x20600 0x100>; interrupts = ; - clocks = <&clk_periph>; + clocks = <&periph_clk>; }; - gic: interrupt-controller@1000 { + gic: interrupt-controller@21000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x1000 0x1000>, - <0x0100 0x100>; + reg = <0x21000 0x1000>, + <0x20100 0x100>; }; - L2: cache-controller@2000 { + L2: cache-controller@22000 { compatible = "arm,pl310-cache"; - reg = <0x2000 0x1000>; + reg = <0x22000 0x1000>; cache-unified; arm,shared-override; prefetch-data = <1>; @@ -94,14 +102,37 @@ clocks { #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges; - /* As long as we do not have a real clock driver us this - * fixed clock */ - clk_periph: periph { + osc: oscillator { + #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + periph_clk: periph_clk { #clock-cells = <0>; - clock-frequency = <400000000>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; }; }; @@ -178,6 +209,25 @@ }; }; + lcpll0: lcpll0@1800c100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x1800c100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", "sdio", + "ddr_phy"; + }; + + genpll: genpll@1800c140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x1800c140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", "ethernetclk", + "usbclk", "iprocfast", "sata1", + "sata2"; + }; + nand: nand@18028000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;