From patchwork Wed Nov 18 23:13:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Mason X-Patchwork-Id: 56956 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp2848593lbb; Wed, 18 Nov 2015 15:14:29 -0800 (PST) X-Received: by 10.68.178.1 with SMTP id cu1mr5824015pbc.115.1447888468908; Wed, 18 Nov 2015 15:14:28 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id xm2si7499338pbb.66.2015.11.18.15.14.28; Wed, 18 Nov 2015 15:14:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757361AbbKRXO0 (ORCPT + 28 others); Wed, 18 Nov 2015 18:14:26 -0500 Received: from mail-gw3-out.broadcom.com ([216.31.210.64]:44294 "EHLO mail-gw3-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757178AbbKRXNy (ORCPT ); Wed, 18 Nov 2015 18:13:54 -0500 X-IronPort-AV: E=Sophos;i="5.20,315,1444719600"; d="scan'208";a="80779696" Received: from irvexchcas08.broadcom.com (HELO IRVEXCHCAS08.corp.ad.broadcom.com) ([10.9.208.57]) by mail-gw3-out.broadcom.com with ESMTP; 18 Nov 2015 15:45:16 -0800 Received: from IRVEXCHSMTP3.corp.ad.broadcom.com (10.9.207.53) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.3.235.1; Wed, 18 Nov 2015 15:13:53 -0800 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP3.corp.ad.broadcom.com (10.9.207.53) with Microsoft SMTP Server id 14.3.235.1; Wed, 18 Nov 2015 15:13:52 -0800 Received: from venom.rtp.broadcom.com (unknown [10.27.64.103]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id AC40E40FE6; Wed, 18 Nov 2015 15:10:38 -0800 (PST) From: Jon Mason To: Florian Fainelli , Hauke Mehrtens , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , "Russell King" CC: , , , Subject: [PATCH 2/3] ARM: dts: enable clock support for Broadcom NSP Date: Wed, 18 Nov 2015 18:13:49 -0500 Message-ID: <1447888430-4451-3-git-send-email-jonmason@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1447888430-4451-1-git-send-email-jonmason@broadcom.com> References: <1447888430-4451-1-git-send-email-jonmason@broadcom.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Replace current device tree dummy clocks with real clock support for Broadcom Northstar Plus SoC Signed-off-by: Jon Mason --- arch/arm/boot/dts/bcm-nsp.dtsi | 99 ++++++++++++++++++++++++++++++++---------- 1 file changed, 75 insertions(+), 24 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 4bcdd28..f85a4f1 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -32,6 +32,7 @@ #include #include +#include #include "skeleton.dtsi" @@ -42,7 +43,7 @@ mpcore { compatible = "simple-bus"; - ranges = <0x00000000 0x19020000 0x00003000>; + ranges = <0x00000000 0x19000000 0x00023000>; #address-cells = <1>; #size-cells = <1>; @@ -58,32 +59,23 @@ }; }; - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x2000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - gic: interrupt-controller@19021000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1000 0x1000>, - <0x0100 0x100>; + a9pll: arm_clk@19000000 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x00000 0x1000>; }; timer@19020200 { compatible = "arm,cortex-a9-global-timer"; - reg = <0x0200 0x100>; + reg = <0x20200 0x100>; interrupts = ; clocks = <&periph_clk>; }; twd-timer@19020600 { compatible = "arm,cortex-a9-twd-timer"; - reg = <0x0600 0x20>; + reg = <0x20600 0x20>; interrupts = ; clocks = <&periph_clk>; @@ -91,11 +83,27 @@ twd-watchdog@19020620 { compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x0620 0x20>; + reg = <0x20620 0x20>; interrupts = ; clocks = <&periph_clk>; }; + + gic: interrupt-controller@19021000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + cache-level = <2>; + }; }; clocks { @@ -103,10 +111,34 @@ #size-cells = <1>; ranges; - periph_clk: periph_clk { + osc: oscillator { + #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + periph_clk: periph_clk { #clock-cells = <0>; - clock-frequency = <500000000>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; }; }; @@ -118,17 +150,17 @@ uart0: serial@18000300 { compatible = "ns16550a"; - reg = <0x0300 0x100>; + reg = <0x000300 0x100>; interrupts = ; - clock-frequency = <62499840>; + clocks = <&osc>; status = "disabled"; }; uart1: serial@18000400 { compatible = "ns16550a"; - reg = <0x0400 0x100>; + reg = <0x000400 0x100>; interrupts = ; - clock-frequency = <62499840>; + clocks = <&osc>; status = "disabled"; }; @@ -217,5 +249,24 @@ brcm,nand-has-wp; }; + + lcpll0: lcpll0@1803f100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x03f100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", "sdio", + "ddr_phy"; + }; + + genpll: genpll@1803f140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x03f140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", "ethernetclk", + "usbclk", "iprocfast", "sata1", + "sata2"; + }; }; };