From patchwork Tue Nov 17 19:55:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Mason X-Patchwork-Id: 56863 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp2146718lbb; Tue, 17 Nov 2015 11:56:06 -0800 (PST) X-Received: by 10.66.155.197 with SMTP id vy5mr65717672pab.109.1447790166420; Tue, 17 Nov 2015 11:56:06 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id di4si59942032pbc.31.2015.11.17.11.56.06; Tue, 17 Nov 2015 11:56:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754764AbbKQTz5 (ORCPT + 28 others); Tue, 17 Nov 2015 14:55:57 -0500 Received: from mail-gw3-out.broadcom.com ([216.31.210.64]:54817 "EHLO mail-gw3-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754609AbbKQTzc (ORCPT ); Tue, 17 Nov 2015 14:55:32 -0500 X-IronPort-AV: E=Sophos;i="5.20,309,1444719600"; d="scan'208";a="80623083" Received: from irvexchcas07.broadcom.com (HELO IRVEXCHCAS07.corp.ad.broadcom.com) ([10.9.208.55]) by mail-gw3-out.broadcom.com with ESMTP; 17 Nov 2015 12:26:44 -0800 Received: from IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) by IRVEXCHCAS07.corp.ad.broadcom.com (10.9.208.55) with Microsoft SMTP Server (TLS) id 14.3.235.1; Tue, 17 Nov 2015 11:55:31 -0800 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) with Microsoft SMTP Server id 14.3.235.1; Tue, 17 Nov 2015 11:55:31 -0800 Received: from venom.rtp.broadcom.com (unknown [10.27.64.103]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 6A5DC40FE9; Tue, 17 Nov 2015 11:52:15 -0800 (PST) From: Jon Mason To: Florian Fainelli , Rob Herring , Pawel Moll , Mark Rutland , "Ian Campbell" , Kumar Gala , Russell King CC: , , , Subject: [PATCH 1/2] ARM: dts: NSP: Device Tree clean-ups Date: Tue, 17 Nov 2015 14:55:26 -0500 Message-ID: <1447790127-27237-2-git-send-email-jonmason@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1447790127-27237-1-git-send-email-jonmason@broadcom.com> References: <1447790127-27237-1-git-send-email-jonmason@broadcom.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Minor changes to the Broadcom Northstar Plus device tree to make it more organized and clean. Firstly, move the GIC and L2 cache entries to be sequential with respect to the memory addresses. Secondly, modify the address portion of the entry names to reflect the difference from the range modification. Signed-off-by: Jon Mason --- arch/arm/boot/dts/bcm-nsp.dtsi | 50 +++++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 25 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 4bcdd28..7335a74 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -58,30 +58,14 @@ }; }; - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x2000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - gic: interrupt-controller@19021000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1000 0x1000>, - <0x0100 0x100>; - }; - - timer@19020200 { + timer@0200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x0200 0x100>; interrupts = ; clocks = <&periph_clk>; }; - twd-timer@19020600 { + twd-timer@0600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x0600 0x20>; interrupts = ; }; - twd-watchdog@19020620 { + twd-watchdog@0620 { compatible = "arm,cortex-a9-twd-wdt"; reg = <0x0620 0x20>; interrupts = ; clocks = <&periph_clk>; }; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x0100 0x100>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0x2000 0x1000>; + cache-unified; + cache-level = <2>; + }; }; clocks { @@ -116,7 +116,7 @@ #address-cells = <1>; #size-cells = <1>; - uart0: serial@18000300 { + uart0: serial@0300 { compatible = "ns16550a"; reg = <0x0300 0x100>; interrupts = ; @@ -124,7 +124,7 @@ status = "disabled"; }; - uart1: serial@18000400 { + uart1: serial@0400 { compatible = "ns16550a"; reg = <0x0400 0x100>; interrupts = ; @@ -132,7 +132,7 @@ status = "disabled"; }; - pcie0: pcie@18012000 { + pcie0: pcie@12000 { compatible = "brcm,iproc-pcie"; reg = <0x12000 0x1000>; @@ -156,7 +156,7 @@ status = "disabled"; }; - pcie1: pcie@18013000 { + pcie1: pcie@13000 { compatible = "brcm,iproc-pcie"; reg = <0x13000 0x1000>; @@ -180,7 +180,7 @@ status = "disabled"; }; - pcie2: pcie@18014000 { + pcie2: pcie@14000 { compatible = "brcm,iproc-pcie"; reg = <0x14000 0x1000>; @@ -204,7 +204,7 @@ status = "disabled"; }; - nand: nand@18026000 { + nand: nand@26000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x026000 0x600>, <0x11b408 0x600>,