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[184.64.168.246]) by smtp.gmail.com with ESMTPSA id xi7sm21737967pbc.56.2015.11.13.10.46.48 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Nov 2015 10:46:49 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net, nicolas.pitre@linaro.org Cc: adrian.hunter@intel.com, zhang.chunyan@linaro.org, mike.leach@arm.com, tor@ti.com, al.grant@arm.com, pawel.moll@arm.com, fainelli@broadcom.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org Subject: [PATCH V4 21/26] coresight: introducing a global trace ID function Date: Fri, 13 Nov 2015 11:45:12 -0700 Message-Id: <1447440317-1977-22-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1447440317-1977-1-git-send-email-mathieu.poirier@linaro.org> References: <1447440317-1977-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TraceID values have to be unique for all tracers and consistent between drivers and user space. As such introducing a central function to be used whenever a traceID value is required. The patch also account for data traceIDs, which are usually I(N) + 1. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm3x.c | 7 ++----- include/linux/coresight-pmu.h | 12 ++++++++++++ 2 files changed, 14 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index c07b7d3eee86..ebd569986bd4 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -784,11 +785,7 @@ static void etm_init_arch_data(void *info) static void etm_init_trace_id(struct etm_drvdata *drvdata) { - /* - * A trace ID of value 0 is invalid, so let's start at some - * random value that fits in 7 bits and go from there. - */ - drvdata->traceid = 0x10 + drvdata->cpu; + drvdata->traceid = coresight_get_trace_id(drvdata->cpu); } static int etm_probe(struct amba_device *adev, const struct amba_id *id) diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 6c5386b23b10..7d410260661b 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -19,9 +19,21 @@ #define _LINUX_CORESIGHT_PMU_H #define CORESIGHT_ETM_PMU_NAME "cs_etm" +#define CORESIGHT_ETM_PMU_SEED 0x10 /* ETMv3.5/PTM's ETMCR config bit */ #define ETM_OPT_CYCACC 12 #define ETM_OPT_TS 28 +static inline int coresight_get_trace_id(int cpu) +{ + /* + * A trace ID of value 0 is invalid, so let's start at some + * random value that fits in 7 bits and go from there. Since + * the common convention is to have data trace IDs be I(N) + 1, + * set instruction trace IDs as a function of the CPU number. + */ + return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); +} + #endif