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[209.132.180.67]) by mx.google.com with ESMTP id cz6si15247281pad.187.2015.11.11.14.24.41; Wed, 11 Nov 2015 14:24:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=neutral (body hash did not verify) header.i=@linaro_org.20150623.gappssmtp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753320AbbKKWYi (ORCPT + 28 others); Wed, 11 Nov 2015 17:24:38 -0500 Received: from mail-pa0-f52.google.com ([209.85.220.52]:33964 "EHLO mail-pa0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753058AbbKKWTm (ORCPT ); Wed, 11 Nov 2015 17:19:42 -0500 Received: by padhx2 with SMTP id hx2so42985175pad.1 for ; Wed, 11 Nov 2015 14:19:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro_org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vNXwL1Vmvy6gRlkIM0ym8VMaudelNbiYK08V5ksvWu8=; b=YHPPSzIxE2QHCDuxGnQdfxPF9wXR5jEd8J58E3PGhlBLBDshQyN+ijzYeP2q5AwrUq d6dcQqA72B31nQG2sM6xZ3cU/cDIpf9ce0WGTgyVVMu6fGXPlxzIaiY2VU9+JSVkxwPw pcxK4MIQymorB1i3QlQyYljpnKywajKIJo3hctdowtN4jitCI43BJP/YMUvVn5GzyBMO DEmNk1Z1GlxEuYVqmoL2HIkxR8aLTCXRT4f8Z1s/wsuM1tzw0lHynd3RCaFKVKzDhs6N bA4SErZL2U1wi3vk3BakKJy5fNZcynQqvDBrM67rLa1K62fhY1sojnUTubU7sDqgZEyu Ts8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vNXwL1Vmvy6gRlkIM0ym8VMaudelNbiYK08V5ksvWu8=; b=fhQfuyfJgz0fOdbB+nWF6LyIdPcnoi5PcCX3Iz+rd6IZIG3M7eEUU7T8GMbfvu3UuM u70ThZrjgtDwHBaarnTtYAiJ7XkfGz3qJkfliNdUkLZDYSWVQFUaiI5XyH/mVtmtQ0os kjBt5pSr+pKaznixPcf0hrKKQ+ng44HisXGXtsqUoNHP0PqkEsPo2p2tHUSJ0rbvGddB QReccu+SauIKfgjJ0aOUVP5WdC0Ysg0AKz0pEZhH8sIjwEwzTaFKWXOI20u06A/GAHTw 7vnKzVjp7dYuo+xgIVc9u3O6tQZG7owOhom5nSlv8PHQQgVFYye0Fp6bB+qn9nCIUNGW gFzw== X-Gm-Message-State: ALoCoQnXokaQHAJm9Fxk8QxM0BL0MNXyrZKUT6HZZKfxPfDAs1hc9a23OVVKZeG8juWHrtuk8TG2 X-Received: by 10.66.62.138 with SMTP id y10mr17612277par.129.1447280382031; Wed, 11 Nov 2015 14:19:42 -0800 (PST) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id h10sm11156697pat.7.2015.11.11.14.19.40 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Nov 2015 14:19:41 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net, nicolas.pitre@linaro.org Cc: adrian.hunter@intel.com, zhang.chunyan@linaro.org, mike.leach@arm.com, tor@ti.com, al.grant@arm.com, pawel.moll@arm.com, fainelli@broadcom.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org Subject: [PATCH V3 14/26] coresight: etm3x: adding perf_get/set_config() API Date: Wed, 11 Nov 2015 15:18:04 -0700 Message-Id: <1447280296-19147-15-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1447280296-19147-1-git-send-email-mathieu.poirier@linaro.org> References: <1447280296-19147-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adding a source operation to build a tracer's configuration from a perf_event. That way possibly complex parsing of the information conveyed by the event doesn't have to be carried out every time the configuration is needed. Since event configuration can change between concurrent sessions, the possibility of associating a tracer with a configuration is also provided. As such Perf can assign session configuration to tracers as it see fit. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/Kconfig | 1 + drivers/hwtracing/coresight/coresight-etm3x.c | 62 +++++++++++++++++++++++++++ include/linux/coresight.h | 7 ++- 3 files changed, 69 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 6c8921140f02..e252dd1522e5 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -4,6 +4,7 @@ menuconfig CORESIGHT bool "CoreSight Tracing Support" select ARM_AMBA + select PERF_EVENTS help This framework provides a kernel interface for the CoreSight debug and trace drivers to register themselves with. It's intended to build diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index a83c67d13b21..dd319ef0f1ac 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include "coresight-etm.h" @@ -315,6 +316,40 @@ void etm_config_trace_mode(struct etm_drvdata *drvdata, config->addr_type[1] = ETM_ADDR_TYPE_RANGE; } +#define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN) + +static int etm_parse_event_config(struct etm_drvdata *drvdata, + struct etm_config *config, + struct perf_event *event) +{ + u32 mode = 0; + u64 event_config = event->attr.config; + + if (event->attr.exclude_kernel) + mode = ETM_MODE_EXCL_KERN; + + if (event->attr.exclude_user) + mode = ETM_MODE_EXCL_USER; + + /* + * By default the tracers are configured to trace the whole address + * range. Narrow the field only if requested by user space. + */ + if (mode) + etm_config_trace_mode(drvdata, config, mode); + + /* + * At this time only cycle accurate and timestamp options are + * available. + */ + if (event_config & ~ETM3X_SUPPORTED_OPTIONS) + return -EINVAL; + + config->ctrl = event_config; + + return 0; +} + static void etm_enable_hw(void *info) { int i; @@ -428,6 +463,31 @@ static int etm_trace_id(struct coresight_device *csdev) return etm_get_trace_id(drvdata); } +static void *etm_get_config(struct coresight_device *csdev, + struct perf_event *event) +{ + struct etm_config *config = NULL; + struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + config = kzalloc(sizeof(struct etm_config), GFP_KERNEL); + if (!config) + return config; + + etm_set_default(config); + + if (etm_parse_event_config(drvdata, config, event)) + return ERR_PTR(-EINVAL); + + return config; +} + +static void etm_set_config(struct coresight_device *csdev, void *config) +{ + struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + drvdata->config = config; +} + static int etm_enable_sysfs(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -568,6 +628,8 @@ static void etm_disable(struct coresight_device *csdev) static const struct coresight_ops_source etm_source_ops = { .cpu_id = etm_cpu_id, .trace_id = etm_trace_id, + .get_config = etm_get_config, + .set_config = etm_set_config, .enable = etm_enable, .disable = etm_disable, }; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 61dfb8d511ea..f2148bc2bcfe 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -206,13 +206,18 @@ struct coresight_ops_link { * @cpu_id: returns the value of the CPU number this component * is associated to. * @trace_id: returns the value of the component's trace ID as known - to the HW. + * to the HW. + * @get_config: builds the ETM configuration after events' specifics. + * @set_config: associate a tracer with a configuration. * @enable: enables tracing for a source. * @disable: disables tracing for a source. */ struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); int (*trace_id)(struct coresight_device *csdev); + void *(*get_config)(struct coresight_device *csdev, + struct perf_event *event); + void (*set_config)(struct coresight_device *csdev, void *config); int (*enable)(struct coresight_device *csdev, u32 mode); void (*disable)(struct coresight_device *csdev); };