From patchwork Fri Nov 6 08:28:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "majun \(F\)" X-Patchwork-Id: 56100 Delivered-To: patch@linaro.org Received: by 10.112.61.134 with SMTP id p6csp883454lbr; Fri, 6 Nov 2015 00:50:30 -0800 (PST) X-Received: by 10.66.187.6 with SMTP id fo6mr586139pac.41.1446799830581; Fri, 06 Nov 2015 00:50:30 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b10si16288123pbu.142.2015.11.06.00.50.30; Fri, 06 Nov 2015 00:50:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757318AbbKFItp (ORCPT + 28 others); Fri, 6 Nov 2015 03:49:45 -0500 Received: from szxga03-in.huawei.com ([119.145.14.66]:44563 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754933AbbKFItn (ORCPT ); Fri, 6 Nov 2015 03:49:43 -0500 Received: from 172.24.1.49 (EHLO szxeml432-hub.china.huawei.com) ([172.24.1.49]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BQM85346; Fri, 06 Nov 2015 16:28:58 +0800 (CST) Received: from localhost (10.177.235.245) by szxeml432-hub.china.huawei.com (10.82.67.209) with Microsoft SMTP Server id 14.3.235.1; Fri, 6 Nov 2015 16:28:49 +0800 From: MaJun To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v8 3/4] irqchip:create irq domain for each mbigen device Date: Fri, 6 Nov 2015 16:28:41 +0800 Message-ID: <1446798522-28000-4-git-send-email-majun258@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1446798522-28000-1-git-send-email-majun258@huawei.com> References: <1446798522-28000-1-git-send-email-majun258@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.235.245] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.563C6895.00B2, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ed0032d63fc6c80d6d28ab8bdf650a13 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ma Jun For peripheral devices which connect to mbigen,mbigen is a interrupt controller. So, we create irq domain for each mbigen device and add mbigen irq domain into irq hierarchy structure. Signed-off-by: Ma Jun --- drivers/irqchip/irq-mbigen.c | 163 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 163 insertions(+), 0 deletions(-) -- 1.7.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c index 25e4000..71291cb 100644 --- a/drivers/irqchip/irq-mbigen.c +++ b/drivers/irqchip/irq-mbigen.c @@ -16,27 +16,176 @@ * along with this program. If not, see . */ +#include +#include #include +#include #include #include #include #include #include +/* Interrupt numbers per mbigen node supported */ +#define IRQS_PER_MBIGEN_NODE 128 + +/* 16 irqs (Pin0-pin15) are reserved for each mbigen chip */ +#define RESERVED_IRQ_PER_MBIGEN_CHIP 16 + +/** + * In mbigen vector register + * bit[21:12]: event id value + * bit[11:0]: device id + */ +#define IRQ_EVENT_ID_SHIFT 12 +#define IRQ_EVENT_ID_MASK 0x3ff + +/* register range of each mbigen node */ +#define MBIGEN_NODE_OFFSET 0x1000 + +/* offset of vector register in mbigen node */ +#define REG_MBIGEN_VEC_OFFSET 0x200 + + /** * struct mbigen_device - holds the information of mbigen device. * * @pdev: pointer to the platform device structure of mbigen chip. * @base: mapped address of this mbigen chip. + * @domain: pointer to the irq domain */ struct mbigen_device { struct platform_device *pdev; void __iomem *base; + struct irq_domain *domain; +}; + +/** + * struct mbigen_irq_data - private data of each irq + * + * @base: mapped address of mbigen chip + * @reg_vec: addr offset of interrupt vector register. + */ +struct mbigen_irq_data { + void __iomem *base; + unsigned int reg_vec; +}; + +static inline int get_mbigen_vec_reg(u32 nid, u32 offset) +{ + return (offset * 4) + nid * MBIGEN_NODE_OFFSET + + REG_MBIGEN_VEC_OFFSET; +} + +static struct irq_chip mbigen_irq_chip = { + .name = "mbigen-v2", +}; + +static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + struct mbigen_irq_data *mgn_irq_data = irq_get_chip_data(desc->irq); + u32 val; + + val = readl_relaxed(mgn_irq_data->reg_vec + mgn_irq_data->base); + + val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT); + val |= (msg->data << IRQ_EVENT_ID_SHIFT); + + writel_relaxed(val, mgn_irq_data->reg_vec + mgn_irq_data->base); +} + +static struct mbigen_irq_data *set_mbigen_irq_data(int hwirq) +{ + struct mbigen_irq_data *datap; + unsigned int nid, pin_offset; + + datap = kzalloc(sizeof(*datap), GFP_KERNEL); + if (!datap) + return NULL; + + /* get the mbigen node number */ + nid = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) / IRQS_PER_MBIGEN_NODE + 1; + + pin_offset = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) + % IRQS_PER_MBIGEN_NODE; + + datap->reg_vec = get_mbigen_vec_reg(nid, pin_offset); + return datap; +} + +static int mbigen_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + if (is_of_node(fwspec->fwnode)) { + if (fwspec->param_count != 2) + return -EINVAL; + + *hwirq = fwspec->param[0]; + *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + + return 0; + } + return -EINVAL; +} + +static int mbigen_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, + void *args) +{ + struct irq_fwspec *fwspec = args; + irq_hw_number_t hwirq; + unsigned int type; + struct mbigen_device *mgn_chip; + struct mbigen_irq_data *mgn_irq_data; + int i, err; + + err = mbigen_domain_translate(domain, fwspec, &hwirq, &type); + if (err) + return err; + + err = platform_msi_domain_alloc(domain, virq, nr_irqs); + if (err) + return err; + + /* set related information of this irq */ + mgn_irq_data = set_mbigen_irq_data(hwirq); + if (!mgn_irq_data) + return err; + + mgn_chip = platform_msi_get_host_data(domain); + mgn_irq_data->base = mgn_chip->base; + + for (i = 0; i < nr_irqs; i++) + irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, + &mbigen_irq_chip, mgn_irq_data); + + return 0; +} + +static void mbigen_domain_free(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct mbigen_irq_data *mgn_irq_data = irq_data_get_irq_chip_data(d); + + kfree(mgn_irq_data); + irq_domain_free_irqs_common(domain, virq, nr_irqs); +} + +static struct irq_domain_ops mbigen_domain_ops = { + .translate = mbigen_domain_translate, + .alloc = mbigen_irq_domain_alloc, + .free = mbigen_domain_free, }; static int mbigen_device_probe(struct platform_device *pdev) { struct mbigen_device *mgn_chip; + struct irq_domain *domain; + u32 num_msis; mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL); if (!mgn_chip) @@ -45,6 +194,20 @@ static int mbigen_device_probe(struct platform_device *pdev) mgn_chip->pdev = pdev; mgn_chip->base = of_iomap(pdev->dev.of_node, 0); + /* If there is no "num-msi" property, assume 64... */ + if (of_property_read_u32(pdev->dev.of_node, "num-msis", &num_msis) < 0) + num_msis = 64; + + domain = platform_msi_create_device_domain(&pdev->dev, num_msis, + mbigen_write_msg, + &mbigen_domain_ops, + mgn_chip); + + if (!domain) + return -ENOMEM; + + mgn_chip->domain = domain; + platform_set_drvdata(pdev, mgn_chip); return 0;