From patchwork Fri Oct 23 22:15:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 55510 Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp1487150lbq; Fri, 23 Oct 2015 15:16:23 -0700 (PDT) X-Received: by 10.66.145.10 with SMTP id sq10mr7183595pab.114.1445638583136; Fri, 23 Oct 2015 15:16:23 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ya7si32597125pbc.121.2015.10.23.15.16.22; Fri, 23 Oct 2015 15:16:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752791AbbJWWQR (ORCPT + 28 others); Fri, 23 Oct 2015 18:16:17 -0400 Received: from mail-lf0-f46.google.com ([209.85.215.46]:36276 "EHLO mail-lf0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751324AbbJWWQN (ORCPT ); Fri, 23 Oct 2015 18:16:13 -0400 Received: by lffz202 with SMTP id z202so98243688lff.3 for ; Fri, 23 Oct 2015 15:16:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KR4JeY6CR+4uXQsk0Tww8Ysta+c8wbRqWMgy+YKoGdQ=; b=V6xWlEQRm4C9fT6LiiXOynzxF7AVxAEjivwRvHLmPf2kwUby1ZIAa2uG1bDNS3COiD vLqonb6nz3U1I1rpIl6OQcjvjHci/34E4UEoeU1T8w2/1MuAJmLF+9qagu3piIN24Yk5 WJpQ4xpkIbEtakVeWlwEy5247QKDXoBURd8+BniyM+SXK2WtesIhAycpFaQ+SuHce/3i hvQXorCHtQX2dDlGPBDSggqH0iCnoxHl1HUM7q3soIt7xonMB2XZx+fl9KqjckHJdvX8 693m4qCl6X0raXPJTqBEFntZvRsAST9eCYRe00fH3H62nfAgAIF15x80mlFfhBTMC96F F58A== X-Gm-Message-State: ALoCoQn3bfbmmymBaIO/lS3fzVIKYBcF0CyozEKJGdL2LbFc4d+UcGayZDWboHUSXCQfxkOvzxsh X-Received: by 10.112.158.38 with SMTP id wr6mr12402972lbb.25.1445638571458; Fri, 23 Oct 2015 15:16:11 -0700 (PDT) Received: from localhost.localdomain.localdomain (c-297471d5.01-192-6c756e10.cust.bredbandsbolaget.se. [213.113.116.41]) by smtp.gmail.com with ESMTPSA id f77sm3062710lfi.3.2015.10.23.15.16.10 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Oct 2015 15:16:10 -0700 (PDT) From: Linus Walleij To: Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: linux-kernel@vger.kernel.org, Linus Walleij Subject: [PATCH 2/3] irqchip/gic: support RealView variant setup Date: Sat, 24 Oct 2015 00:15:52 +0200 Message-Id: <1445638553-8825-2-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1445638553-8825-1-git-send-email-linus.walleij@linaro.org> References: <1445638553-8825-1-git-send-email-linus.walleij@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ARM RealView PB11MPCore reference design has some special bits in a system controller register to set up the GIC in one of three modes: legacy, new with DCC, new without DCC. The register is also used to enable FIQ. Since the platform will not boot unless this register is set up to "new with DCC" mode, we need a special quirk to be compiled-in for the RealView platforms. If we find the right compatible string on the GIC TestChip, we enable this quirk by looking up the system controller and enabling the special bits. We depend on the CONFIG_REALVIEW_DT Kconfig symbol as the old boardfile code has the same fix hardcoded, and this is only needed for the attempts to modernize the RealView code using device tree. After fixing this, the PB11MPCore boots with device tree only. Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Put the IRQCHIP_DECLARE() in the add-on irq-gic-realview.c file and have it call down to gic_of_init() after its special initialization - Created irq-gic.h to export functions inside irq-gic.c. Part of me wanted to use irq-gic-common.h so as not to proliferate the header files, but I felt it was encapsulating the functions in irq-gic-common.c so it seemed dirty, better to give irq-gic.c its own header file. - Broke out this irqchip stuff from the rest of the series so as not to stress the irqchip maintainers. It has no dependencies on the other patches anyways, and can be merged stand-alone. --- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-gic-realview.c | 43 ++++++++++++++++++++++++++++++++++++++ drivers/irqchip/irq-gic.c | 3 ++- drivers/irqchip/irq-gic.h | 7 +++++++ 4 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 drivers/irqchip/irq-gic-realview.c create mode 100644 drivers/irqchip/irq-gic.h -- 2.4.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index bb3048f00e64..7a7d4182777d 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o +obj-$(CONFIG_REALVIEW_DT) += irq-gic-realview.o obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o diff --git a/drivers/irqchip/irq-gic-realview.c b/drivers/irqchip/irq-gic-realview.c new file mode 100644 index 000000000000..bb5583c07667 --- /dev/null +++ b/drivers/irqchip/irq-gic-realview.c @@ -0,0 +1,43 @@ +/* + * Special GIC quirks for the ARM RealView + * Copyright (C) 2015 Linus Walleij + */ +#include +#include +#include +#include +#include + +#include "irq-gic.h" + +#define REALVIEW_SYS_LOCK_OFFSET 0x20 +#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74 +#define VERSATILE_LOCK_VAL 0xA05F +#define PLD_INTMODE_MASK BIT(22)|BIT(23)|BIT(24) +#define PLD_INTMODE_LEGACY 0x0 +#define PLD_INTMODE_NEW_DCC BIT(22) +#define PLD_INTMODE_NEW_NO_DCC BIT(23) +#define PLD_INTMODE_FIQ_ENABLE BIT(24) + +static int __init +realview_gic_of_init(struct device_node *node, struct device_node *parent) +{ + static struct regmap *map; + + /* The PB11MPCore GIC needs to be configured in the syscon */ + map = syscon_regmap_lookup_by_compatible("arm,realview-pb11mp-syscon"); + if (!IS_ERR(map)) { + /* new irq mode with no DCC */ + regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, + VERSATILE_LOCK_VAL); + regmap_update_bits(map, REALVIEW_PB11MP_SYS_PLD_CTRL1, + PLD_INTMODE_NEW_NO_DCC, + PLD_INTMODE_MASK); + regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000); + pr_info("TC11MP GIC: set up interrupt controller to NEW mode, no DCC\n"); + } else { + pr_err("TC11MP GIC setup: could not find syscon\n"); + } + return gic_of_init(node, parent); +} +IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init); diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 982c09c2d791..9ec8cf5137d9 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -50,6 +50,7 @@ #include #include "irq-gic-common.h" +#include "irq-gic.h" union gic_base { void __iomem *common_base; @@ -1141,7 +1142,7 @@ static bool gic_check_eoimode(struct device_node *node, void __iomem **base) return true; } -static int __init +int __init gic_of_init(struct device_node *node, struct device_node *parent) { void __iomem *cpu_base; diff --git a/drivers/irqchip/irq-gic.h b/drivers/irqchip/irq-gic.h new file mode 100644 index 000000000000..3c45a540c235 --- /dev/null +++ b/drivers/irqchip/irq-gic.h @@ -0,0 +1,7 @@ +#include + +/* + * Subdrivers that need some preparatory work can initialize their + * chips and call this to register their GICs. + */ +int gic_of_init(struct device_node *node, struct device_node *parent);