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[209.132.180.67]) by mx.google.com with ESMTP id e7si17418865igg.14.2015.10.20.01.47.15; Tue, 20 Oct 2015 01:47:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932297AbbJTIrE (ORCPT + 28 others); Tue, 20 Oct 2015 04:47:04 -0400 Received: from szxga01-in.huawei.com ([58.251.152.64]:18404 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752872AbbJTIq5 (ORCPT ); Tue, 20 Oct 2015 04:46:57 -0400 Received: from 172.24.1.51 (EHLO szxeml422-hub.china.huawei.com) ([172.24.1.51]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CXE55701; Tue, 20 Oct 2015 16:42:14 +0800 (CST) Received: from localhost (10.177.235.245) by szxeml422-hub.china.huawei.com (10.82.67.152) with Microsoft SMTP Server id 14.3.235.1; Tue, 20 Oct 2015 16:42:06 +0800 From: MaJun To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 4/4] irqchip:implement the mbigen irq chip operation functions Date: Tue, 20 Oct 2015 16:42:00 +0800 Message-ID: <1445330520-11960-5-git-send-email-majun258@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1445330520-11960-1-git-send-email-majun258@huawei.com> References: <1445330520-11960-1-git-send-email-majun258@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.235.245] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: majun258@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Ma Jun Add the interrupt controller chip operation functions of mbigen chip. Signed-off-by: Ma Jun --- drivers/irqchip/irq-mbigen.c | 100 +++++++++++++++++++++++++++++++++++++++-- 1 files changed, 95 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c index 211b3c8..dbda7bc 100644 --- a/drivers/irqchip/irq-mbigen.c +++ b/drivers/irqchip/irq-mbigen.c @@ -45,6 +45,21 @@ /* offset of vector register in mbigen node */ #define REG_MBIGEN_VEC_OFFSET 0x200 + +/** + * offset of clear register in mbigen node + * This register is used to clear the status + * of interrupt + */ +#define REG_MBIGEN_CLEAR_OFFSET 0xa00 + +/** + * offset of interrupt type register + * This register is used to configure interrupt + * trigger type + */ +#define REG_MBIGEN_TYPE_OFFSET 0x0 + /** * struct mbigen_device - holds the information of mbigen device. * @@ -62,11 +77,19 @@ struct mbigen_device { * struct mbigen_irq_data - private data of each irq * * @base: mapped address of mbigen chip + * @pin_offset: local pin offset of interrupt. * @reg_vec: addr offset of interrupt vector register. + * @reg_type: addr offset of interrupt trigger type register. + * @reg_clear: addr offset of interrupt clear register. + * @type: interrupt trigger type. */ struct mbigen_irq_data { void __iomem *base; + unsigned int pin_offset; unsigned int reg_vec; + unsigned int reg_type; + unsigned int reg_clear; + unsigned int type; }; static inline int get_mbigen_vec_reg(u32 nid, u32 offset) @@ -75,6 +98,61 @@ static inline int get_mbigen_vec_reg(u32 nid, u32 offset) + REG_MBIGEN_VEC_OFFSET; } +static int get_mbigen_type_reg(u32 nid, u32 offset) +{ + int ofst; + + ofst = offset / 32 * 4; + return ofst + nid * MBIGEN_NODE_OFFSET + + REG_MBIGEN_TYPE_OFFSET; +} + +static int get_mbigen_clear_reg(u32 nid, u32 offset) +{ + int ofst; + + ofst = offset / 32 * 4; + return ofst + nid * MBIGEN_NODE_OFFSET + + REG_MBIGEN_CLEAR_OFFSET; +} + +static void mbigen_eoi_irq(struct irq_data *data) +{ + struct mbigen_irq_data *mgn_irq_data = irq_data_get_irq_chip_data(data); + u32 mask; + + /* only level triggered interrupt need to clear status */ + if (mgn_irq_data->type == IRQ_TYPE_LEVEL_HIGH) { + mask = 1 << (mgn_irq_data->pin_offset % 32); + writel_relaxed(mask, mgn_irq_data->reg_clear + mgn_irq_data->base); + } + + irq_chip_eoi_parent(data); +} + +static int mbigen_set_type(struct irq_data *d, unsigned int type) +{ + struct mbigen_irq_data *mgn_irq_data = irq_data_get_irq_chip_data(d); + u32 mask; + int val; + + if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) + return -EINVAL; + + mask = 1 << (mgn_irq_data->pin_offset % 32); + + val = readl_relaxed(mgn_irq_data->reg_type + mgn_irq_data->base); + + if (type == IRQ_TYPE_LEVEL_HIGH) + val |= mask; + else if (type == IRQ_TYPE_EDGE_RISING) + val &= ~mask; + + writel_relaxed(val, mgn_irq_data->reg_type + mgn_irq_data->base); + + return 0; +} + static struct irq_chip mbigen_irq_chip = { .name = "mbigen-v2", .irq_mask = irq_chip_mask_parent, @@ -97,10 +175,11 @@ static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg) writel_relaxed(val, mgn_irq_data->reg_vec + mgn_irq_data->base); } -static struct mbigen_irq_data *set_mbigen_irq_data(int hwirq) +static struct mbigen_irq_data *set_mbigen_irq_data(int hwirq, + unsigned int type) { struct mbigen_irq_data *datap; - unsigned int nid, pin_offset; + unsigned int nid; datap = kzalloc(sizeof(*datap), GFP_KERNEL); if (!datap) @@ -109,10 +188,20 @@ static struct mbigen_irq_data *set_mbigen_irq_data(int hwirq) /* get the mbigen node number */ nid = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) / IRQS_PER_MBIGEN_NODE + 1; - pin_offset = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) + datap->pin_offset = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) % IRQS_PER_MBIGEN_NODE; - datap->reg_vec = get_mbigen_vec_reg(nid, pin_offset); + datap->reg_type = get_mbigen_type_reg(nid, datap->pin_offset); + datap->reg_vec = get_mbigen_vec_reg(nid, datap->pin_offset); + + /* no clear register for edge triggered interrupt */ + if (type == IRQ_TYPE_EDGE_RISING) + datap->reg_clear = 0; + else + datap->reg_clear = get_mbigen_clear_reg(nid, + datap->pin_offset); + + datap->type = type; return datap; } @@ -140,6 +229,7 @@ static int mbigen_irq_domain_alloc(struct irq_domain *domain, { struct irq_fwspec *fwspec = args; irq_hw_number_t hwirq = fwspec->param[0]; + unsigned int type = fwspec->param[1]; struct mbigen_device *mgn_chip; struct mbigen_irq_data *mgn_irq_data; int i, err; @@ -149,7 +239,7 @@ static int mbigen_irq_domain_alloc(struct irq_domain *domain, return err; /* set related information of this irq */ - mgn_irq_data = set_mbigen_irq_data(hwirq); + mgn_irq_data = set_mbigen_irq_data(hwirq, type); if (!mgn_irq_data) return err;