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[209.132.180.67]) by mx.google.com with ESMTP id l1si1932070igx.70.2015.10.20.01.46.52; Tue, 20 Oct 2015 01:46:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753151AbbJTIqt (ORCPT + 28 others); Tue, 20 Oct 2015 04:46:49 -0400 Received: from szxga01-in.huawei.com ([58.251.152.64]:18072 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752872AbbJTIql (ORCPT ); Tue, 20 Oct 2015 04:46:41 -0400 Received: from 172.24.1.48 (EHLO szxeml434-hub.china.huawei.com) ([172.24.1.48]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CXE55689; Tue, 20 Oct 2015 16:42:12 +0800 (CST) Received: from localhost (10.177.235.245) by szxeml434-hub.china.huawei.com (10.82.67.225) with Microsoft SMTP Server id 14.3.235.1; Tue, 20 Oct 2015 16:42:04 +0800 From: MaJun To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 3/4] irqchip:create irq domain for each mbigen device Date: Tue, 20 Oct 2015 16:41:59 +0800 Message-ID: <1445330520-11960-4-git-send-email-majun258@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1445330520-11960-1-git-send-email-majun258@huawei.com> References: <1445330520-11960-1-git-send-email-majun258@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.235.245] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: majun258@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Ma Jun For peripheral devices which connect to mbigen,mbigen is a interrupt controller. So, we create irq domain for each mbigen device and add mbigen irq domain into irq hierarchy structure. Signed-off-by: Ma Jun --- drivers/irqchip/irq-mbigen.c | 152 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 152 insertions(+), 0 deletions(-) diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c index f18132f..211b3c8 100644 --- a/drivers/irqchip/irq-mbigen.c +++ b/drivers/irqchip/irq-mbigen.c @@ -16,27 +16,164 @@ * along with this program. If not, see . */ +#include +#include #include +#include #include #include #include #include #include +/* Interrupt numbers per mbigen node supported */ +#define IRQS_PER_MBIGEN_NODE 128 + +/* 16 irqs (Pin0-pin15) are reserved for each mbigen chip */ +#define RESERVED_IRQ_PER_MBIGEN_CHIP 16 + +/** + * In mbigen vector register + * bit[21:12]: event id value + * bit[11:0]: device id + */ +#define IRQ_EVENT_ID_SHIFT 12 +#define IRQ_EVENT_ID_MASK 0x3ff + +/* register range of each mbigen node */ +#define MBIGEN_NODE_OFFSET 0x1000 + +/* offset of vector register in mbigen node */ +#define REG_MBIGEN_VEC_OFFSET 0x200 /** * struct mbigen_device - holds the information of mbigen device. * * @pdev: pointer to the platform device structure of mbigen chip. * @base: mapped address of this mbigen chip. + * @domain: pointer to the irq domain */ struct mbigen_device { struct platform_device *pdev; void __iomem *base; + struct irq_domain *domain; +}; + +/** + * struct mbigen_irq_data - private data of each irq + * + * @base: mapped address of mbigen chip + * @reg_vec: addr offset of interrupt vector register. + */ +struct mbigen_irq_data { + void __iomem *base; + unsigned int reg_vec; +}; + +static inline int get_mbigen_vec_reg(u32 nid, u32 offset) +{ + return (offset * 4) + nid * MBIGEN_NODE_OFFSET + + REG_MBIGEN_VEC_OFFSET; +} + +static struct irq_chip mbigen_irq_chip = { + .name = "mbigen-v2", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_eoi = mbigen_eoi_irq, + .irq_set_type = mbigen_set_type, + .irq_set_affinity = irq_chip_set_affinity_parent, +}; + +static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + struct mbigen_irq_data *mgn_irq_data = irq_get_chip_data(desc->irq); + u32 val; + + val = readl_relaxed(mgn_irq_data->reg_vec + mgn_irq_data->base); + + val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT); + val |= (msg->data << IRQ_EVENT_ID_SHIFT); + + writel_relaxed(val, mgn_irq_data->reg_vec + mgn_irq_data->base); +} + +static struct mbigen_irq_data *set_mbigen_irq_data(int hwirq) +{ + struct mbigen_irq_data *datap; + unsigned int nid, pin_offset; + + datap = kzalloc(sizeof(*datap), GFP_KERNEL); + if (!datap) + return NULL; + + /* get the mbigen node number */ + nid = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) / IRQS_PER_MBIGEN_NODE + 1; + + pin_offset = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) + % IRQS_PER_MBIGEN_NODE; + + datap->reg_vec = get_mbigen_vec_reg(nid, pin_offset); + return datap; +} + +static int mbigen_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + if (is_of_node(fwspec->fwnode)) { + if (fwspec->param_count != 2) + return -EINVAL; + + *hwirq = fwspec->param[0]; + *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + + return 0; + } + return -EINVAL; +} + +static int mbigen_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, + void *args) +{ + struct irq_fwspec *fwspec = args; + irq_hw_number_t hwirq = fwspec->param[0]; + struct mbigen_device *mgn_chip; + struct mbigen_irq_data *mgn_irq_data; + int i, err; + + err = platform_msi_domain_alloc(domain, virq, nr_irqs); + if (err) + return err; + + /* set related information of this irq */ + mgn_irq_data = set_mbigen_irq_data(hwirq); + if (!mgn_irq_data) + return err; + + mgn_chip = platform_msi_get_host_data(domain); + mgn_irq_data->base = mgn_chip->base; + + for (i = 0; i < nr_irqs; i++) + irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, + &mbigen_irq_chip, mgn_irq_data); + + return 0; +} + +static struct irq_domain_ops mbigen_domain_ops = { + .translate = mbigen_domain_translate, + .alloc = mbigen_irq_domain_alloc, + .free = irq_domain_free_irqs_common, }; static int mbigen_device_probe(struct platform_device *pdev) { struct mbigen_device *mgn_chip; + struct irq_domain *domain; + u32 num_msis; mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL); if (!mgn_chip) @@ -45,6 +182,20 @@ static int mbigen_device_probe(struct platform_device *pdev) mgn_chip->pdev = pdev; mgn_chip->base = of_iomap(pdev->dev.of_node, 0); + /* If there is no "num-msi" property, assume 64... */ + if (of_property_read_u32(pdev->dev.of_node, "num-msis", &num_msis) < 0) + num_msis = 64; + + domain = platform_msi_create_device_domain(&pdev->dev, num_msis, + mbigen_write_msg, + &mbigen_domain_ops, + mgn_chip); + + if (!domain) + return -ENOMEM; + + mgn_chip->domain = domain; + platform_set_drvdata(pdev, mgn_chip); return 0; @@ -54,6 +205,7 @@ static int mbigen_device_remove(struct platform_device *pdev) { struct mbigen_device *mgn_chip = platform_get_drvdata(pdev); + irq_domain_remove(mgn_chip->domain); iounmap(mgn_chip->base); return 0;