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[209.132.180.67]) by mx.google.com with ESMTP id d3si28434595pbu.219.2015.10.12.12.48.00; Mon, 12 Oct 2015 12:48:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932106AbbJLTro (ORCPT + 30 others); Mon, 12 Oct 2015 15:47:44 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:50846 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751661AbbJLTrj (ORCPT ); Mon, 12 Oct 2015 15:47:39 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id t9CJkmPb022245; Mon, 12 Oct 2015 14:46:49 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t9CJkmYw022312; Mon, 12 Oct 2015 14:46:48 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Mon, 12 Oct 2015 14:46:47 -0500 Received: from ula0868495.am.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t9CJkjeS018403; Mon, 12 Oct 2015 14:46:47 -0500 From: Murali Karicheri To: , , , , , , , , , , , , Subject: [PATCH 1/4] Documentation: dt: soc: move driver description to a separate document Date: Mon, 12 Oct 2015 15:46:48 -0400 Message-ID: <1444679211-823-2-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444679211-823-1-git-send-email-m-karicheri2@ti.com> References: <1444679211-823-1-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: m-karicheri2@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.169 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Currently the DT bindings have details about the driver as well. This patch moves this to a separate document for knav qmss driver so that driver detail update can be done as needed without polluting the DT bindings description. Signed-off-by: Murali Karicheri --- Documentation/arm/keystone/knav-qmss.txt | 24 ++++++++++++++++++++++ .../bindings/soc/ti/keystone-navigator-qmss.txt | 20 ++++-------------- 2 files changed, 28 insertions(+), 16 deletions(-) create mode 100644 Documentation/arm/keystone/knav-qmss.txt diff --git a/Documentation/arm/keystone/knav-qmss.txt b/Documentation/arm/keystone/knav-qmss.txt new file mode 100644 index 0000000..79946d1 --- /dev/null +++ b/Documentation/arm/keystone/knav-qmss.txt @@ -0,0 +1,24 @@ +* Texas Instruments Keystone Navigator Queue Management SubSystem driver + +Driver source code path + drivers/soc/ti/knav_qmss.c + drivers/soc/ti/knav_qmss_acc.c + +The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of +the main hardware sub system which forms the backbone of the Keystone +multi-core Navigator. QMSS consist of queue managers, packed-data structure +processors(PDSP), linking RAM, descriptor pools and infrastructure +Packet DMA. +The Queue Manager is a hardware module that is responsible for accelerating +management of the packet queues. Packets are queued/de-queued by writing or +reading descriptor address to a particular memory mapped location. The PDSPs +perform QMSS related functions like accumulation, QoS, or event management. +Linking RAM registers are used to link the descriptors which are stored in +descriptor RAM. Descriptor RAM is configurable as internal or external memory. +The QMSS driver manages the PDSP setups, linking RAM regions, +queue pool management (allocation, push, pop and notify) and descriptor +pool management. + +knav qmss driver provides a set of APIs to drivers to open/close qmss queues, +allocate descriptor pools, map the descriptors, push/pop to queues etc. For +details of the available APIs, please refers to include/linux/soc/ti/knav_qmss.h diff --git a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt index d8e8cdb..2cecea1 100644 --- a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt +++ b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt @@ -1,20 +1,8 @@ -* Texas Instruments Keystone Navigator Queue Management SubSystem driver - -The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of -the main hardware sub system which forms the backbone of the Keystone -multi-core Navigator. QMSS consist of queue managers, packed-data structure -processors(PDSP), linking RAM, descriptor pools and infrastructure -Packet DMA. -The Queue Manager is a hardware module that is responsible for accelerating -management of the packet queues. Packets are queued/de-queued by writing or -reading descriptor address to a particular memory mapped location. The PDSPs -perform QMSS related functions like accumulation, QoS, or event management. -Linking RAM registers are used to link the descriptors which are stored in -descriptor RAM. Descriptor RAM is configurable as internal or external memory. -The QMSS driver manages the PDSP setups, linking RAM regions, -queue pool management (allocation, push, pop and notify) and descriptor -pool management. +* Texas Instruments Keystone Navigator (knav) Queue Management SubSystem driver + DT bindings +For details of the driver, please refer to +Documentation/arm/keystone/knav-qmss.txt Required properties: - compatible : Must be "ti,keystone-navigator-qmss";