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[209.132.180.67]) by mx.google.com with ESMTP id gn6si401630pbc.40.2015.09.30.02.45.26; Wed, 30 Sep 2015 02:45:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932163AbbI3JpZ (ORCPT + 30 others); Wed, 30 Sep 2015 05:45:25 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:9307 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754744AbbI3JpN (ORCPT ); Wed, 30 Sep 2015 05:45:13 -0400 Received: from 172.24.1.49 (EHLO szxeml431-hub.china.huawei.com) ([172.24.1.49]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BOE74990; Wed, 30 Sep 2015 17:39:22 +0800 (CST) Received: from localhost (10.177.235.245) by szxeml431-hub.china.huawei.com (10.82.67.208) with Microsoft SMTP Server id 14.3.235.1; Wed, 30 Sep 2015 17:39:15 +0800 From: MaJun To: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 3/3] dt-binding:Documents of the mbigen bindings Date: Wed, 30 Sep 2015 17:39:09 +0800 Message-ID: <1443605949-15396-4-git-send-email-majun258@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1443605949-15396-1-git-send-email-majun258@huawei.com> References: <1443605949-15396-1-git-send-email-majun258@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.235.245] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.560BAEA7.0012, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 17beb7bb2d6844bac4147288bcc7a3a7 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: majun258@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Ma Jun Add the mbigen msi interrupt controller bindings document. This patch based on Mark Rutland's patch https://lkml.org/lkml/2015/7/23/558 Signed-off-by: Ma Jun --- Documentation/devicetree/bindings/arm/mbigen.txt | 85 ++++++++++++++++++++++ 1 files changed, 85 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mbigen.txt diff --git a/Documentation/devicetree/bindings/arm/mbigen.txt b/Documentation/devicetree/bindings/arm/mbigen.txt new file mode 100644 index 0000000..f5345ab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mbigen.txt @@ -0,0 +1,85 @@ +Hisilicon mbigen device tree bindings. +======================================= + +Mbigen means: message based interrupt generator. + +MBI is kind of msi interrupt only used on Non-PCI devices. + +To reduce the wired interrupt number connected to GIC, +Hisilicon designed mbigen to collect and generate interrupt. + + +Non-pci devices can connect to mbigen and generate the +interrupt by writing ITS register. + +The mbigen chip and devices connect to mbigen have the following properties: + +Mbigen main node required properties: +------------------------------------------- +- compatible: Should be "hisilicon,mbigen-v2" +- reg: Specifies the base physical address and size of the Mbigen + registers. + +Sub-nodes: +--------------------------------------------- +Mbigen has one or more mbigen device nodes which represents the devices +connected to this mbigen chip. + +These nodes must have the following properties: +- compatible: Should be "hisilicon,mbigen-intc-v2" +- interrupt controller: Identifies the node as an interrupt controller +- msi-parent: This property has two cells. + The 1st cell specifies the ITS this device connected. + The 2nd cell specifies the device id. +- nr-interrupts:Specifies the total number of interrupt this device has. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value is 2 now. + + The 1st cell is global hardware pin number of the interrupt. + This value depends on the Soc design. + The 2nd the private index of the device. For a device with n interrupts, + this value is from 0 ~ n-1. + +Examples: + + mbigen_dsa: interrupt-controller@c0080000 { + compatible = "hisilicon,mbigen-v2"; + reg = <0xc0080000 0x10000>; + + mbigen_device_gmac0 { + compatible = "hisilicon,mbigen-intc-v2"; + interrupt-controller; + msi-parent = <&its 0x40b1c>; + nr-interrupts = <9>; + #interrupt-cells = <2>; + } + + mbigen_device_02 { + compatible = "hisilicon,mbigen-intc-v2"; + interrupt-controller; + msi-parent = <&its 0x40b1d>; + nr-interrupts = <3>; + #interrupt-cells = <2>; + } + }; + +Device connect to mbigen required properties: +---------------------------------------------------- +-interrupt-parent: Specifies the mbigen device node which device connected. +-interrupts:specifies the interrupt source. + The 1st cell is global hardware pin number of the interrupt. + This value depends on the Soc design. + The 2nd the private index of the device. For a device with n interrupts, + this value is from 0 ~ n-1. + +Examples: + gmac0: ethernet@c2080000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xc2080000 0 0x20000>, + <0 0xc0000000 0 0x1000>; + interrupt-parent = <&mbigen_device_gmac0>; + interrupts = <656 0>, + <657 1>; + }; +