From patchwork Thu Sep 3 19:23:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 53049 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f199.google.com (mail-wi0-f199.google.com [209.85.212.199]) by patches.linaro.org (Postfix) with ESMTPS id 1C35722E23 for ; Thu, 3 Sep 2015 19:24:21 +0000 (UTC) Received: by wisv5 with SMTP id v5sf6366642wis.0 for ; Thu, 03 Sep 2015 12:24:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :mime-version:content-type:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=lbasubf/Ci20wYGWWBcXxHWHn9J6dbqaSH2vsGVDG4o=; b=gNGE7g2MDYYTXy741wWBhhDDxbsOA3jcDrkIzNof3k20jUE5WHdoZAWeiPJxEiRzmz 8hGtFckNFIZiXeBLm5V9d8rxK4AzOFymja776sBE4WHtHfhiaGyee3nvHF/CZjI1gx5l +f9taMkJyFxn4ndgk2n8pJwbRSFd3pdRk6pYZ2QbYquZWjmRy8y/1LPTYnjqdeiNeK87 8tKA1/4avbDNcFXL6xbC2KxTd7Qss7FLVnytPMVbupaKVHZv92JVg8a9nbXuc1fmYPLf 3Tyg/fIeZR+Clw50GQDbfNKS/zSO1rsVsLl8yAuAjEe9ChEfVKD1b6zD4tBTIbphXygZ qnOw== X-Gm-Message-State: ALoCoQlYxBoJFea0gW+kdXoTFsE2zEd+CLAg6GOOVIs2NJZ4sXch00BKXdm0MlWQSKg0yaC4OpHq X-Received: by 10.112.139.137 with SMTP id qy9mr11071342lbb.17.1441308260402; Thu, 03 Sep 2015 12:24:20 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.27.100 with SMTP id s4ls253107lag.83.gmail; Thu, 03 Sep 2015 12:24:20 -0700 (PDT) X-Received: by 10.112.160.73 with SMTP id xi9mr23192482lbb.92.1441308260117; Thu, 03 Sep 2015 12:24:20 -0700 (PDT) Received: from mail-lb0-f173.google.com (mail-lb0-f173.google.com. [209.85.217.173]) by mx.google.com with ESMTPS id c5si3168822lbp.10.2015.09.03.12.24.20 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2015 12:24:20 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) client-ip=209.85.217.173; Received: by lbcao8 with SMTP id ao8so30205170lbc.3 for ; Thu, 03 Sep 2015 12:24:20 -0700 (PDT) X-Received: by 10.152.43.198 with SMTP id y6mr14968426lal.41.1441308259972; Thu, 03 Sep 2015 12:24:19 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.164.42 with SMTP id yn10csp1475631lbb; Thu, 3 Sep 2015 12:24:19 -0700 (PDT) X-Received: by 10.66.243.70 with SMTP id ww6mr72328030pac.88.1441308258906; Thu, 03 Sep 2015 12:24:18 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id sj1si27038891pac.48.2015.09.03.12.24.17; Thu, 03 Sep 2015 12:24:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752736AbbICTYQ (ORCPT + 8 others); Thu, 3 Sep 2015 15:24:16 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:53071 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752574AbbICTYP (ORCPT ); Thu, 3 Sep 2015 15:24:15 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t83JNnAU000319; Thu, 3 Sep 2015 14:23:49 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t83JNmDx022801; Thu, 3 Sep 2015 14:23:48 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.224.2; Thu, 3 Sep 2015 14:23:49 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t83JNmbh031526; Thu, 3 Sep 2015 14:23:48 -0500 From: Nishanth Menon To: Tony Lindgren , =?UTF-8?q?Beno=C3=AEt=20Cousson?= CC: , , , , Tomi Valkeinen , Nishanth Menon Subject: [PATCH] ARM: dts: am57xx-beagle-x15: Update Phy supplies Date: Thu, 3 Sep 2015 14:23:45 -0500 Message-ID: <1441308226-26690-1-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: nm@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Originally, all the SoC PHY rails were supplied by LDO3. However, as a result of characterization, it was determined that this posed a risk in extreme load conditions. Hence the PHY rails are split between two different LDOs. Update the related node as a result LDO3/VDDA_1V8_PHYA supplies vdda_usb1, vdda_usb2, vdda_sata, vdda_usb3 LDO4/VDDA_1V8_PHYB supplies vdda_pcie1, vdda_pcie0, vdda_hdmi, vdda_pcie NOTE: We break compatibility with pre-production boards with this change since, the PMIC LDO4 is disabled at OTP level. The new configuration is the plan of record and all pre-production boards are supposed to be replaced with the latest boards matching the mentioned configuration. Signed-off-by: Nishanth Menon --- arch/arm/boot/dts/am57xx-beagle-x15.dts | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index 3a05b94f59ed..ede7fb73c717 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -432,7 +432,7 @@ }; ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ + /* VDDA_1V8_PHYA */ regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -440,6 +440,15 @@ regulator-boot-on; }; + ldo4_reg: ldo4 { + /* VDDA_1V8_PHYB */ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo9_reg: ldo9 { /* VDD_RTC */ regulator-name = "ldo9"; @@ -681,7 +690,7 @@ &hdmi { status = "ok"; - vdda-supply = <&ldo3_reg>; + vdda-supply = <&ldo4_reg>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_pins>;