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[78.210.255.2]) by smtp.gmail.com with ESMTPSA id jr5sm28598154wjc.14.2015.08.10.02.54.52 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 10 Aug 2015 02:54:52 -0700 (PDT) From: Daniel Lezcano To: mingo@kernel.org Cc: tglx@linutronix.de, linux-kernel@vger.kernel.org, Viresh Kumar , Steven Miao , adi-buildroot-devel@lists.sourceforge.net Subject: [PATCH 60/74] blackfin/time-ts: Migrate to new 'set-state' interface Date: Mon, 10 Aug 2015 11:52:17 +0200 Message-Id: <1439200352-26767-60-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1439200352-26767-1-git-send-email-daniel.lezcano@linaro.org> References: <55C87382.4070309@linaro.org> <1439200352-26767-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.lezcano@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Viresh Kumar Migrate blackfin driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. We weren't doing anything in ->set_mode(RESUME) and so tick_resume() isn't implemented. Cc: Steven Miao Cc: adi-buildroot-devel@lists.sourceforge.net Signed-off-by: Viresh Kumar Signed-off-by: Daniel Lezcano --- arch/blackfin/kernel/time-ts.c | 136 +++++++++++++++++++++-------------------- 1 file changed, 70 insertions(+), 66 deletions(-) diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c index cb0a484..fb9e95f 100644 --- a/arch/blackfin/kernel/time-ts.c +++ b/arch/blackfin/kernel/time-ts.c @@ -136,44 +136,44 @@ static int bfin_gptmr0_set_next_event(unsigned long cycles, return 0; } -static void bfin_gptmr0_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) +static int bfin_gptmr0_set_periodic(struct clock_event_device *evt) { - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: { #ifndef CONFIG_BF60x - set_gptimer_config(TIMER0_id, \ - TIMER_OUT_DIS | TIMER_IRQ_ENA | \ - TIMER_PERIOD_CNT | TIMER_MODE_PWM); + set_gptimer_config(TIMER0_id, + TIMER_OUT_DIS | TIMER_IRQ_ENA | + TIMER_PERIOD_CNT | TIMER_MODE_PWM); #else - set_gptimer_config(TIMER0_id, TIMER_OUT_DIS - | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER); + set_gptimer_config(TIMER0_id, + TIMER_OUT_DIS | TIMER_MODE_PWM_CONT | + TIMER_PULSE_HI | TIMER_IRQ_PER); #endif - set_gptimer_period(TIMER0_id, get_sclk() / HZ); - set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1); - enable_gptimers(TIMER0bit); - break; - } - case CLOCK_EVT_MODE_ONESHOT: - disable_gptimers(TIMER0bit); + set_gptimer_period(TIMER0_id, get_sclk() / HZ); + set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1); + enable_gptimers(TIMER0bit); + return 0; +} + +static int bfin_gptmr0_set_oneshot(struct clock_event_device *evt) +{ + disable_gptimers(TIMER0bit); #ifndef CONFIG_BF60x - set_gptimer_config(TIMER0_id, \ - TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM); + set_gptimer_config(TIMER0_id, + TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM); #else - set_gptimer_config(TIMER0_id, TIMER_OUT_DIS | TIMER_MODE_PWM - | TIMER_PULSE_HI | TIMER_IRQ_WID_DLY); + set_gptimer_config(TIMER0_id, + TIMER_OUT_DIS | TIMER_MODE_PWM | TIMER_PULSE_HI | + TIMER_IRQ_WID_DLY); #endif - set_gptimer_period(TIMER0_id, 0); - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - disable_gptimers(TIMER0bit); - break; - case CLOCK_EVT_MODE_RESUME: - break; - } + set_gptimer_period(TIMER0_id, 0); + return 0; +} + +static int bfin_gptmr0_shutdown(struct clock_event_device *evt) +{ + disable_gptimers(TIMER0bit); + return 0; } static void bfin_gptmr0_ack(void) @@ -211,13 +211,16 @@ static struct irqaction gptmr0_irq = { }; static struct clock_event_device clockevent_gptmr0 = { - .name = "bfin_gptimer0", - .rating = 300, - .irq = IRQ_TIMER0, - .shift = 32, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = bfin_gptmr0_set_next_event, - .set_mode = bfin_gptmr0_set_mode, + .name = "bfin_gptimer0", + .rating = 300, + .irq = IRQ_TIMER0, + .shift = 32, + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = bfin_gptmr0_set_next_event, + .set_state_shutdown = bfin_gptmr0_shutdown, + .set_state_periodic = bfin_gptmr0_set_periodic, + .set_state_oneshot = bfin_gptmr0_set_oneshot, }; static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt) @@ -250,36 +253,35 @@ static int bfin_coretmr_set_next_event(unsigned long cycles, return 0; } -static void bfin_coretmr_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) +static int bfin_coretmr_set_periodic(struct clock_event_device *evt) { - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: { - unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1); - bfin_write_TCNTL(TMPWR); - CSYNC(); - bfin_write_TSCALE(TIME_SCALE - 1); - bfin_write_TPERIOD(tcount); - bfin_write_TCOUNT(tcount); - CSYNC(); - bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD); - break; - } - case CLOCK_EVT_MODE_ONESHOT: - bfin_write_TCNTL(TMPWR); - CSYNC(); - bfin_write_TSCALE(TIME_SCALE - 1); - bfin_write_TPERIOD(0); - bfin_write_TCOUNT(0); - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - bfin_write_TCNTL(0); - CSYNC(); - break; - case CLOCK_EVT_MODE_RESUME: - break; - } + unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1); + + bfin_write_TCNTL(TMPWR); + CSYNC(); + bfin_write_TSCALE(TIME_SCALE - 1); + bfin_write_TPERIOD(tcount); + bfin_write_TCOUNT(tcount); + CSYNC(); + bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD); + return 0; +} + +static int bfin_coretmr_set_oneshot(struct clock_event_device *evt) +{ + bfin_write_TCNTL(TMPWR); + CSYNC(); + bfin_write_TSCALE(TIME_SCALE - 1); + bfin_write_TPERIOD(0); + bfin_write_TCOUNT(0); + return 0; +} + +static int bfin_coretmr_shutdown(struct clock_event_device *evt) +{ + bfin_write_TCNTL(0); + CSYNC(); + return 0; } void bfin_coretmr_init(void) @@ -335,7 +337,9 @@ void bfin_coretmr_clockevent_init(void) evt->shift = 32; evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; evt->set_next_event = bfin_coretmr_set_next_event; - evt->set_mode = bfin_coretmr_set_mode; + evt->set_state_shutdown = bfin_coretmr_shutdown; + evt->set_state_periodic = bfin_coretmr_set_periodic; + evt->set_state_oneshot = bfin_coretmr_set_oneshot; clock_tick = get_cclk() / TIME_SCALE; evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);