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[209.85.215.45]) by mx.google.com with ESMTPS id xi9si14695107lbb.4.2015.05.06.05.48.23 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 May 2015 05:48:23 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) client-ip=209.85.215.45; Received: by layy10 with SMTP id y10so6506236lay.0 for ; Wed, 06 May 2015 05:48:23 -0700 (PDT) X-Received: by 10.152.2.227 with SMTP id 3mr27987008lax.73.1430916503040; Wed, 06 May 2015 05:48:23 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.67.65 with SMTP id l1csp2835619lbt; Wed, 6 May 2015 05:48:22 -0700 (PDT) X-Received: by 10.70.8.163 with SMTP id s3mr24324449pda.154.1430916501082; Wed, 06 May 2015 05:48:21 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id am5si28923450pbc.14.2015.05.06.05.48.19; Wed, 06 May 2015 05:48:21 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752131AbbEFMsP (ORCPT + 29 others); Wed, 6 May 2015 08:48:15 -0400 Received: from mail-la0-f43.google.com ([209.85.215.43]:35260 "EHLO mail-la0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750833AbbEFMsM (ORCPT ); Wed, 6 May 2015 08:48:12 -0400 Received: by labbd9 with SMTP id bd9so6451726lab.2 for ; Wed, 06 May 2015 05:48:10 -0700 (PDT) X-Received: by 10.152.27.98 with SMTP id s2mr28492156lag.106.1430916490276; Wed, 06 May 2015 05:48:10 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id aj4sm351775lbd.5.2015.05.06.05.48.08 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 May 2015 05:48:09 -0700 (PDT) From: Linus Walleij To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH] pinctrl: nomadik: assign chips dynamically Date: Wed, 6 May 2015 14:48:04 +0200 Message-Id: <1430916484-7756-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Assign GPIO chip and irqchip to the GPIO container dynamically, so we can set a unique name for each GPIO irqchip and see what chip the hwirq offset actually relates to. Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-nomadik.c | 61 +++++++++++++++---------------- 1 file changed, 30 insertions(+), 31 deletions(-) diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index a6a22054c0ba..c37093c8659c 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -246,6 +246,7 @@ enum nmk_gpio_slpm { struct nmk_gpio_chip { struct gpio_chip chip; + struct irq_chip irqchip; void __iomem *addr; struct clk *clk; unsigned int bank; @@ -842,18 +843,6 @@ static void nmk_gpio_irq_shutdown(struct irq_data *d) clk_disable(nmk_chip->clk); } -static struct irq_chip nmk_gpio_irq_chip = { - .name = "Nomadik-GPIO", - .irq_ack = nmk_gpio_irq_ack, - .irq_mask = nmk_gpio_irq_mask, - .irq_unmask = nmk_gpio_irq_unmask, - .irq_set_type = nmk_gpio_irq_set_type, - .irq_set_wake = nmk_gpio_irq_set_wake, - .irq_startup = nmk_gpio_irq_startup, - .irq_shutdown = nmk_gpio_irq_shutdown, - .flags = IRQCHIP_MASK_ON_SUSPEND, -}; - static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, u32 status) { @@ -1077,18 +1066,6 @@ static inline void nmk_gpio_dbg_show_one(struct seq_file *s, #define nmk_gpio_dbg_show NULL #endif -/* This structure is replicated for each GPIO block allocated at probe time */ -static struct gpio_chip nmk_gpio_template = { - .request = nmk_gpio_request, - .free = nmk_gpio_free, - .direction_input = nmk_gpio_make_input, - .get = nmk_gpio_get_input, - .direction_output = nmk_gpio_make_output, - .set = nmk_gpio_set_output, - .dbg_show = nmk_gpio_dbg_show, - .can_sleep = false, -}; - void nmk_gpio_clocks_enable(void) { int i; @@ -1190,6 +1167,7 @@ static int nmk_gpio_probe(struct platform_device *dev) struct device_node *np = dev->dev.of_node; struct nmk_gpio_chip *nmk_chip; struct gpio_chip *chip; + struct irq_chip *irqchip; struct resource *res; struct clk *clk; int latent_irq; @@ -1236,19 +1214,40 @@ static int nmk_gpio_probe(struct platform_device *dev) nmk_chip->bank = dev->id; nmk_chip->clk = clk; nmk_chip->addr = base; - nmk_chip->chip = nmk_gpio_template; nmk_chip->parent_irq = irq; nmk_chip->latent_parent_irq = latent_irq; nmk_chip->sleepmode = supports_sleepmode; spin_lock_init(&nmk_chip->lock); chip = &nmk_chip->chip; + chip->request = nmk_gpio_request; + chip->free = nmk_gpio_free; + chip->direction_input = nmk_gpio_make_input; + chip->get = nmk_gpio_get_input; + chip->direction_output = nmk_gpio_make_output; + chip->set = nmk_gpio_set_output; + chip->dbg_show = nmk_gpio_dbg_show; + chip->can_sleep = false; chip->base = dev->id * NMK_GPIO_PER_CHIP; chip->ngpio = NMK_GPIO_PER_CHIP; chip->label = dev_name(&dev->dev); chip->dev = &dev->dev; chip->owner = THIS_MODULE; + irqchip = &nmk_chip->irqchip; + irqchip->irq_ack = nmk_gpio_irq_ack; + irqchip->irq_mask = nmk_gpio_irq_mask; + irqchip->irq_unmask = nmk_gpio_irq_unmask; + irqchip->irq_set_type = nmk_gpio_irq_set_type; + irqchip->irq_set_wake = nmk_gpio_irq_set_wake; + irqchip->irq_startup = nmk_gpio_irq_startup; + irqchip->irq_shutdown = nmk_gpio_irq_shutdown; + irqchip->flags = IRQCHIP_MASK_ON_SUSPEND; + irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u", + dev->id, + chip->base, + chip->base + chip->ngpio - 1); + clk_enable(nmk_chip->clk); nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); clk_disable(nmk_chip->clk); @@ -1269,8 +1268,8 @@ static int nmk_gpio_probe(struct platform_device *dev) * handler will perform the actual work of handling the parent * interrupt. */ - ret = gpiochip_irqchip_add(&nmk_chip->chip, - &nmk_gpio_irq_chip, + ret = gpiochip_irqchip_add(chip, + irqchip, 0, handle_edge_irq, IRQ_TYPE_EDGE_FALLING); @@ -1280,13 +1279,13 @@ static int nmk_gpio_probe(struct platform_device *dev) return -ENODEV; } /* Then register the chain on the parent IRQ */ - gpiochip_set_chained_irqchip(&nmk_chip->chip, - &nmk_gpio_irq_chip, + gpiochip_set_chained_irqchip(chip, + irqchip, nmk_chip->parent_irq, nmk_gpio_irq_handler); if (nmk_chip->latent_parent_irq > 0) - gpiochip_set_chained_irqchip(&nmk_chip->chip, - &nmk_gpio_irq_chip, + gpiochip_set_chained_irqchip(chip, + irqchip, nmk_chip->latent_parent_irq, nmk_gpio_latent_irq_handler);