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[209.132.180.67]) by mx.google.com with ESMTP id e5si21755228pdf.253.2015.03.18.06.32.43; Wed, 18 Mar 2015 06:32:44 -0700 (PDT) Received-SPF: none (google.com: linux-arm-msm-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933165AbbCRNcQ (ORCPT + 5 others); Wed, 18 Mar 2015 09:32:16 -0400 Received: from mail-wg0-f46.google.com ([74.125.82.46]:36275 "EHLO mail-wg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933135AbbCRNcJ (ORCPT ); Wed, 18 Mar 2015 09:32:09 -0400 Received: by wgra20 with SMTP id a20so35378025wgr.3 for ; Wed, 18 Mar 2015 06:32:08 -0700 (PDT) X-Received: by 10.180.98.131 with SMTP id ei3mr6935610wib.62.1426685527997; Wed, 18 Mar 2015 06:32:07 -0700 (PDT) Received: from mms.wifi.mm-sol.com ([37.157.136.206]) by mx.google.com with ESMTPSA id cf12sm24531838wjb.10.2015.03.18.06.32.06 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 18 Mar 2015 06:32:07 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org, mturquette@linaro.org Cc: galak@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v1 5/9] clk: qcom: Convert apq8084 to parent_map tables Date: Wed, 18 Mar 2015 15:32:11 +0200 Message-Id: <1426685535-25071-6-git-send-email-georgi.djakov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1426685535-25071-1-git-send-email-georgi.djakov@linaro.org> References: <1426685535-25071-1-git-send-email-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: georgi.djakov@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Signed-off-by: Georgi Djakov --- drivers/clk/qcom/gcc-apq8084.c | 70 ++++++++------- drivers/clk/qcom/mmcc-apq8084.c | 178 +++++++++++++++++++++------------------ 2 files changed, 134 insertions(+), 114 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c index e3ef90264214..f75b505a13b8 100644 --- a/drivers/clk/qcom/gcc-apq8084.c +++ b/drivers/clk/qcom/gcc-apq8084.c @@ -32,18 +32,21 @@ #include "clk-branch.h" #include "reset.h" -#define P_XO 0 -#define P_GPLL0 1 -#define P_GPLL1 1 -#define P_GPLL4 2 -#define P_PCIE_0_1_PIPE_CLK 1 -#define P_SATA_ASIC0_CLK 1 -#define P_SATA_RX_CLK 1 -#define P_SLEEP_CLK 1 - -static const u8 gcc_xo_gpll0_map[] = { - [P_XO] = 0, - [P_GPLL0] = 1, +enum { + P_XO, + P_GPLL0, + P_GPLL1, + P_GPLL4, + P_PCIE_0_1_PIPE_CLK, + P_SATA_ASIC0_CLK, + P_SATA_RX_CLK, + P_SLEEP_CLK, +}; + +static const struct parent_map gcc_xo_gpll0_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { } }; static const char *gcc_xo_gpll0[] = { @@ -51,10 +54,11 @@ static const char *gcc_xo_gpll0[] = { "gpll0_vote", }; -static const u8 gcc_xo_gpll0_gpll4_map[] = { - [P_XO] = 0, - [P_GPLL0] = 1, - [P_GPLL4] = 5, +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL4, 5 }, + { } }; static const char *gcc_xo_gpll0_gpll4[] = { @@ -63,9 +67,10 @@ static const char *gcc_xo_gpll0_gpll4[] = { "gpll4_vote", }; -static const u8 gcc_xo_sata_asic0_map[] = { - [P_XO] = 0, - [P_SATA_ASIC0_CLK] = 2, +static const struct parent_map gcc_xo_sata_asic0_map[] = { + { P_XO, 0 }, + { P_SATA_ASIC0_CLK, 2 }, + { } }; static const char *gcc_xo_sata_asic0[] = { @@ -73,9 +78,10 @@ static const char *gcc_xo_sata_asic0[] = { "sata_asic0_clk", }; -static const u8 gcc_xo_sata_rx_map[] = { - [P_XO] = 0, - [P_SATA_RX_CLK] = 2, +static const struct parent_map gcc_xo_sata_rx_map[] = { + { P_XO, 0 }, + { P_SATA_RX_CLK, 2}, + { } }; static const char *gcc_xo_sata_rx[] = { @@ -83,9 +89,10 @@ static const char *gcc_xo_sata_rx[] = { "sata_rx_clk", }; -static const u8 gcc_xo_pcie_map[] = { - [P_XO] = 0, - [P_PCIE_0_1_PIPE_CLK] = 2, +static const struct parent_map gcc_xo_pcie_map[] = { + { P_XO, 0 }, + { P_PCIE_0_1_PIPE_CLK, 2 }, + { } }; static const char *gcc_xo_pcie[] = { @@ -93,9 +100,10 @@ static const char *gcc_xo_pcie[] = { "pcie_pipe", }; -static const u8 gcc_xo_pcie_sleep_map[] = { - [P_XO] = 0, - [P_SLEEP_CLK] = 6, +static const struct parent_map gcc_xo_pcie_sleep_map[] = { + { P_XO, 0 }, + { P_SLEEP_CLK, 6 }, + { } }; static const char *gcc_xo_pcie_sleep[] = { @@ -1263,9 +1271,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = { { } }; -static u8 usb_hsic_clk_src_map[] = { - [P_XO] = 0, - [P_GPLL1] = 4, +static const struct parent_map usb_hsic_clk_src_map[] = { + { P_XO, 0 }, + { P_GPLL1, 4 }, }; static struct clk_rcg2 usb_hsic_clk_src = { diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c index 157139a5c1ca..0fe93fd85a43 100644 --- a/drivers/clk/qcom/mmcc-apq8084.c +++ b/drivers/clk/qcom/mmcc-apq8084.c @@ -27,28 +27,31 @@ #include "clk-branch.h" #include "reset.h" -#define P_XO 0 -#define P_MMPLL0 1 -#define P_EDPLINK 1 -#define P_MMPLL1 2 -#define P_HDMIPLL 2 -#define P_GPLL0 3 -#define P_EDPVCO 3 -#define P_MMPLL4 4 -#define P_DSI0PLL 4 -#define P_DSI0PLL_BYTE 4 -#define P_MMPLL2 4 -#define P_MMPLL3 4 -#define P_GPLL1 5 -#define P_DSI1PLL 5 -#define P_DSI1PLL_BYTE 5 -#define P_MMSLEEP 6 - -static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { - [P_XO] = 0, - [P_MMPLL0] = 1, - [P_MMPLL1] = 2, - [P_GPLL0] = 5, +enum { + P_XO, + P_MMPLL0, + P_EDPLINK, + P_MMPLL1, + P_HDMIPLL, + P_GPLL0, + P_EDPVCO, + P_MMPLL4, + P_DSI0PLL, + P_DSI0PLL_BYTE, + P_MMPLL2, + P_MMPLL3, + P_GPLL1, + P_DSI1PLL, + P_DSI1PLL_BYTE, + P_MMSLEEP, +}; + +static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL1, 2 }, + { P_GPLL0, 5 }, + { } }; static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = { @@ -58,13 +61,14 @@ static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = { "mmss_gpll0_vote", }; -static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { - [P_XO] = 0, - [P_MMPLL0] = 1, - [P_HDMIPLL] = 4, - [P_GPLL0] = 5, - [P_DSI0PLL] = 2, - [P_DSI1PLL] = 3, +static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_HDMIPLL, 4 }, + { P_GPLL0, 5 }, + { P_DSI0PLL, 2 }, + { P_DSI1PLL, 3 }, + { } }; static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { @@ -76,12 +80,13 @@ static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { "dsi1pll", }; -static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = { - [P_XO] = 0, - [P_MMPLL0] = 1, - [P_MMPLL1] = 2, - [P_GPLL0] = 5, - [P_MMPLL2] = 3, +static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL1, 2 }, + { P_GPLL0, 5 }, + { P_MMPLL2, 3 }, + { } }; static const char *mmcc_xo_mmpll0_1_2_gpll0[] = { @@ -92,12 +97,13 @@ static const char *mmcc_xo_mmpll0_1_2_gpll0[] = { "mmpll2", }; -static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = { - [P_XO] = 0, - [P_MMPLL0] = 1, - [P_MMPLL1] = 2, - [P_GPLL0] = 5, - [P_MMPLL3] = 3, +static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL1, 2 }, + { P_GPLL0, 5 }, + { P_MMPLL3, 3 }, + { } }; static const char *mmcc_xo_mmpll0_1_3_gpll0[] = { @@ -108,13 +114,14 @@ static const char *mmcc_xo_mmpll0_1_3_gpll0[] = { "mmpll3", }; -static const u8 mmcc_xo_dsi_hdmi_edp_map[] = { - [P_XO] = 0, - [P_EDPLINK] = 4, - [P_HDMIPLL] = 3, - [P_EDPVCO] = 5, - [P_DSI0PLL] = 1, - [P_DSI1PLL] = 2, +static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = { + { P_XO, 0 }, + { P_EDPLINK, 4 }, + { P_HDMIPLL, 3 }, + { P_EDPVCO, 5 }, + { P_DSI0PLL, 1 }, + { P_DSI1PLL, 2 }, + { } }; static const char *mmcc_xo_dsi_hdmi_edp[] = { @@ -126,13 +133,14 @@ static const char *mmcc_xo_dsi_hdmi_edp[] = { "dsi1pll", }; -static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { - [P_XO] = 0, - [P_EDPLINK] = 4, - [P_HDMIPLL] = 3, - [P_GPLL0] = 5, - [P_DSI0PLL] = 1, - [P_DSI1PLL] = 2, +static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { + { P_XO, 0 }, + { P_EDPLINK, 4 }, + { P_HDMIPLL, 3 }, + { P_GPLL0, 5 }, + { P_DSI0PLL, 1 }, + { P_DSI1PLL, 2 }, + { } }; static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = { @@ -144,13 +152,14 @@ static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = { "dsi1pll", }; -static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { - [P_XO] = 0, - [P_EDPLINK] = 4, - [P_HDMIPLL] = 3, - [P_GPLL0] = 5, - [P_DSI0PLL_BYTE] = 1, - [P_DSI1PLL_BYTE] = 2, +static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { + { P_XO, 0 }, + { P_EDPLINK, 4 }, + { P_HDMIPLL, 3 }, + { P_GPLL0, 5 }, + { P_DSI0PLL_BYTE, 1 }, + { P_DSI1PLL_BYTE, 2 }, + { } }; static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { @@ -162,12 +171,13 @@ static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { "dsi1pllbyte", }; -static const u8 mmcc_xo_mmpll0_1_4_gpll0_map[] = { - [P_XO] = 0, - [P_MMPLL0] = 1, - [P_MMPLL1] = 2, - [P_GPLL0] = 5, - [P_MMPLL4] = 3, +static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL1, 2 }, + { P_GPLL0, 5 }, + { P_MMPLL4, 3 }, + { } }; static const char *mmcc_xo_mmpll0_1_4_gpll0[] = { @@ -178,13 +188,14 @@ static const char *mmcc_xo_mmpll0_1_4_gpll0[] = { "gpll0", }; -static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_map[] = { - [P_XO] = 0, - [P_MMPLL0] = 1, - [P_MMPLL1] = 2, - [P_MMPLL4] = 3, - [P_GPLL0] = 5, - [P_GPLL1] = 4, +static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL1, 2 }, + { P_MMPLL4, 3 }, + { P_GPLL0, 5 }, + { P_GPLL1, 4 }, + { } }; static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = { @@ -196,14 +207,15 @@ static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = { "gpll0", }; -static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = { - [P_XO] = 0, - [P_MMPLL0] = 1, - [P_MMPLL1] = 2, - [P_MMPLL4] = 3, - [P_GPLL0] = 5, - [P_GPLL1] = 4, - [P_MMSLEEP] = 6, +static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL1, 2 }, + { P_MMPLL4, 3 }, + { P_GPLL0, 5 }, + { P_GPLL1, 4 }, + { P_MMSLEEP, 6 }, + { } }; static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {