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X-Original-Sender: georgi.djakov@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.180 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Switch RCG functions to use of the newly introduced parent_map struct. Signed-off-by: Georgi Djakov --- drivers/clk/qcom/clk-rcg.c | 13 ++++++++----- drivers/clk/qcom/clk-rcg.h | 4 ++-- drivers/clk/qcom/clk-rcg2.c | 11 +++++++---- 3 files changed, 17 insertions(+), 11 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c index 64d98c62459d..6eab85882a43 100644 --- a/drivers/clk/qcom/clk-rcg.c +++ b/drivers/clk/qcom/clk-rcg.c @@ -54,7 +54,7 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw) goto err; ns = ns_to_src(&rcg->s, ns); for (i = 0; i < num_parents; i++) - if (ns == rcg->s.parent_map[i]) + if (ns == rcg->s.parent_map[i].cfg) return i; err: @@ -90,7 +90,7 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw) ns = ns_to_src(s, ns); for (i = 0; i < num_parents; i++) - if (ns == s->parent_map[i]) + if (ns == s->parent_map[i].cfg) return i; err: @@ -105,7 +105,7 @@ static int clk_rcg_set_parent(struct clk_hw *hw, u8 index) u32 ns; regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); - ns = src_to_ns(&rcg->s, rcg->s.parent_map[index], ns); + ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns); regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); return 0; @@ -206,7 +206,7 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val) static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f) { u32 ns, md, reg; - int bank, new_bank, ret; + int bank, new_bank, ret, index; struct mn *mn; struct pre_div *p; struct src_sel *s; @@ -275,7 +275,10 @@ static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f) } s = &rcg->s[new_bank]; - ns = src_to_ns(s, s->parent_map[f->src], ns); + index = qcom_find_src_index(s->parent_map, f->src); + if (index < 0) + return index; + ns = src_to_ns(s, s->parent_map[index].cfg, ns); ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); if (ret) return ret; diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 6d94d5300e9e..4a5aa5f125a5 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -76,7 +76,7 @@ struct pre_div { struct src_sel { u8 src_sel_shift; #define SRC_SEL_MASK 0x7 - const u8 *parent_map; + const struct parent_map *parent_map; }; /** @@ -162,7 +162,7 @@ struct clk_rcg2 { u32 cmd_rcgr; u8 mnd_width; u8 hid_width; - const u8 *parent_map; + const struct parent_map *parent_map; const struct freq_tbl *freq_tbl; struct clk_regmap clkr; }; diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 6f27c5c614cc..15cbba3d41fe 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -75,7 +75,7 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw) cfg >>= CFG_SRC_SEL_SHIFT; for (i = 0; i < num_parents; i++) - if (cfg == rcg->parent_map[i]) + if (cfg == rcg->parent_map[i].cfg) return i; err: @@ -117,7 +117,7 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, CFG_SRC_SEL_MASK, - rcg->parent_map[index] << CFG_SRC_SEL_SHIFT); + rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT); if (ret) return ret; @@ -222,7 +222,7 @@ static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate, static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) { u32 cfg, mask; - int ret; + int ret, index; if (rcg->mnd_width && f->n) { mask = BIT(rcg->mnd_width) - 1; @@ -245,7 +245,10 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) mask = BIT(rcg->hid_width) - 1; mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK; cfg = f->pre_div << CFG_SRC_DIV_SHIFT; - cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT; + index = qcom_find_src_index(rcg->parent_map, f->src); + if (index < 0) + return index; + cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; if (rcg->mnd_width && f->n) cfg |= CFG_MODE_DUAL_EDGE; ret = regmap_update_bits(rcg->clkr.regmap,