From patchwork Tue Jan 13 10:26:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 42983 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f71.google.com (mail-wg0-f71.google.com [74.125.82.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 18FBE20DE8 for ; Tue, 13 Jan 2015 10:27:30 +0000 (UTC) Received: by mail-wg0-f71.google.com with SMTP id k14sf1203705wgh.2 for ; Tue, 13 Jan 2015 02:27:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=5pF/84xtJYSHlPTB6C3Rm6v06ZuSxsHdx2arrqDyn4I=; b=CGoFeEIQzZYnr3jNKB7TzDIQBh93ozA//2jKFEkyYrKEpxHS0ibj11HgYKCZMagJZF wvydR/zR9WijrM+RPL1BHe2ur/pj4WHXYVq1whfpunAnW/8M841/bUYirGikyv/Au2Me txWfL1zNOnZE6bwIWiRkyMy24RZWfas8A3ODgxd/UizngYNMUOUS/q79/fq9pPIdu+Ff /ydrpWBU7hN4vxbfncygRF9a57NYGKAnyCtEzEW0WEQfCjqmOBQHK7zqiBInllbsgIl3 vYlAkD9geL76QTegQIDNJKPEduro/Y6rmsVe/kyBD1tuOGnM8hD6BFeSM41l2opCmX3J Q/mw== X-Gm-Message-State: ALoCoQlQCI/izSzjXy5OBzP8jyF1pdP9xxZOhOU0MF3vRDcKQbZaER69Gfb1wxl0X0JXlZByGwhC X-Received: by 10.112.13.161 with SMTP id i1mr162441lbc.20.1421144849408; Tue, 13 Jan 2015 02:27:29 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.5.97 with SMTP id r1ls762827lar.81.gmail; Tue, 13 Jan 2015 02:27:29 -0800 (PST) X-Received: by 10.112.134.74 with SMTP id pi10mr41253701lbb.67.1421144849139; Tue, 13 Jan 2015 02:27:29 -0800 (PST) Received: from mail-la0-f41.google.com (mail-la0-f41.google.com. [209.85.215.41]) by mx.google.com with ESMTPS id d2si2514201laf.39.2015.01.13.02.27.29 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 13 Jan 2015 02:27:29 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.41 as permitted sender) client-ip=209.85.215.41; Received: by mail-la0-f41.google.com with SMTP id hv19so1828809lab.0 for ; Tue, 13 Jan 2015 02:27:28 -0800 (PST) X-Received: by 10.152.5.226 with SMTP id v2mr41659835lav.34.1421144848880; Tue, 13 Jan 2015 02:27:28 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.112.9.200 with SMTP id c8csp1337848lbb; Tue, 13 Jan 2015 02:27:27 -0800 (PST) X-Received: by 10.180.91.37 with SMTP id cb5mr38976711wib.1.1421144847084; Tue, 13 Jan 2015 02:27:27 -0800 (PST) Received: from mail-wg0-f48.google.com (mail-wg0-f48.google.com. [74.125.82.48]) by mx.google.com with ESMTPS id f4si41048634wjy.26.2015.01.13.02.27.26 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 13 Jan 2015 02:27:27 -0800 (PST) Received-SPF: pass (google.com: domain of daniel.thompson@linaro.org designates 74.125.82.48 as permitted sender) client-ip=74.125.82.48; Received: by mail-wg0-f48.google.com with SMTP id l2so2019378wgh.7 for ; Tue, 13 Jan 2015 02:27:26 -0800 (PST) X-Received: by 10.180.72.178 with SMTP id e18mr4053081wiv.23.1421144846816; Tue, 13 Jan 2015 02:27:26 -0800 (PST) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id u18sm25111297wjq.42.2015.01.13.02.27.25 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Jan 2015 02:27:26 -0800 (PST) From: Daniel Thompson To: Thomas Gleixner , Jason Cooper Cc: Daniel Thompson , Russell King , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patches@linaro.org, linaro-kernel@lists.linaro.org, John Stultz , Sumit Semwal , Dirk Behme , Daniel Drake , Dmitry Pervushin , Tim Sander , Stephen Boyd , Marc Zyngier Subject: [PATCH 3.19-rc2 v14 2/7] irqchip: gic: Make gic_raise_softirq FIQ-safe Date: Tue, 13 Jan 2015 10:26:53 +0000 Message-Id: <1421144818-14036-3-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1421144818-14036-1-git-send-email-daniel.thompson@linaro.org> References: <1415968543-29469-1-git-send-email-daniel.thompson@linaro.org> <1421144818-14036-1-git-send-email-daniel.thompson@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.thompson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.41 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , It is currently possible for FIQ handlers to re-enter gic_raise_softirq() and lock up. gic_raise_softirq() lock(x); -~-> FIQ handle_fiq() gic_raise_softirq() lock(x); <-- Lockup arch/arm/ uses IPIs to implement arch_irq_work_raise(), thus this issue renders it difficult for FIQ handlers to safely defer work to less restrictive calling contexts. This patch fixes the problem by converting the cpu_map_migration_lock into a rwlock making it safe to re-enter the function. Note that having made it safe to re-enter gic_raise_softirq() we no longer need to mask interrupts during gic_raise_softirq() because the b.L migration is always performed from task context. Signed-off-by: Daniel Thompson Cc: Thomas Gleixner Cc: Jason Cooper Cc: Russell King Cc: Marc Zyngier --- drivers/irqchip/irq-gic.c | 38 +++++++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index a9ed64dcc84b..c172176499f6 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -75,22 +75,25 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock); /* * This lock is used by the big.LITTLE migration code to ensure no IPIs * can be pended on the old core after the map has been updated. + * + * This lock may be locked for reading from both IRQ and FIQ handlers + * and therefore must not be locked for writing when these are enabled. */ #ifdef CONFIG_BL_SWITCHER -static DEFINE_RAW_SPINLOCK(cpu_map_migration_lock); +static DEFINE_RWLOCK(cpu_map_migration_lock); -static inline void bl_migration_lock(unsigned long *flags) +static inline void bl_migration_lock(void) { - raw_spin_lock_irqsave(&cpu_map_migration_lock, *flags); + read_lock(&cpu_map_migration_lock); } -static inline void bl_migration_unlock(unsigned long flags) +static inline void bl_migration_unlock(void) { - raw_spin_unlock_irqrestore(&cpu_map_migration_lock, flags); + read_unlock(&cpu_map_migration_lock); } #else -static inline void bl_migration_lock(unsigned long *flags) {} -static inline void bl_migration_unlock(unsigned long flags) {} +static inline void bl_migration_lock(void) {} +static inline void bl_migration_unlock(void) {} #endif /* @@ -640,12 +643,20 @@ static void __init gic_pm_init(struct gic_chip_data *gic) #endif #ifdef CONFIG_SMP +/* + * Raise the specified IPI on all cpus set in mask. + * + * This function is safe to call from all calling contexts, including + * FIQ handlers. It relies on bl_migration_lock() being multiply acquirable + * to avoid deadlocks when the function is re-entered at different + * exception levels. + */ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) { int cpu; - unsigned long flags, map = 0; + unsigned long map = 0; - bl_migration_lock(&flags); + bl_migration_lock(); /* Convert our logical CPU mask into a physical one. */ for_each_cpu(cpu, mask) @@ -660,7 +671,7 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) /* this always happens on GIC0 */ writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); - bl_migration_unlock(flags); + bl_migration_unlock(); } #endif @@ -708,7 +719,8 @@ int gic_get_cpu_id(unsigned int cpu) * Migrate all peripheral interrupts with a target matching the current CPU * to the interface corresponding to @new_cpu_id. The CPU interface mapping * is also updated. Targets to other CPU interfaces are unchanged. - * This must be called with IRQs locally disabled. + * This must be called from a task context and with IRQ and FIQ locally + * disabled. */ void gic_migrate_target(unsigned int new_cpu_id) { @@ -739,9 +751,9 @@ void gic_migrate_target(unsigned int new_cpu_id) * pending on the old cpu static. That means we can defer the * migration until after we have released the irq_controller_lock. */ - raw_spin_lock(&cpu_map_migration_lock); + write_lock(&cpu_map_migration_lock); gic_cpu_map[cpu] = 1 << new_cpu_id; - raw_spin_unlock(&cpu_map_migration_lock); + write_unlock(&cpu_map_migration_lock); /* * Find all the peripheral interrupts targetting the current