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[209.132.180.67]) by mx.google.com with ESMTP id lz2si12399317pdb.43.2014.10.21.13.25.17 for ; Tue, 21 Oct 2014 13:25:18 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933576AbaJUUZM (ORCPT + 27 others); Tue, 21 Oct 2014 16:25:12 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:41362 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932529AbaJUUZJ (ORCPT ); Tue, 21 Oct 2014 16:25:09 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s9LKOhLD001905; Tue, 21 Oct 2014 15:24:43 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9LKOhlS019939; Tue, 21 Oct 2014 15:24:43 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Tue, 21 Oct 2014 15:24:44 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9LKOhXC013317; Tue, 21 Oct 2014 15:24:43 -0500 From: Nishanth Menon To: Tony Lindgren , Kevin Hilman CC: , , , Tero Kristo , Nishanth Menon Subject: [PATCH] ARM: OMAP4+: PM: Program CPU logic power state Date: Tue, 21 Oct 2014 15:24:36 -0500 Message-ID: <1413923076-26063-1-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: nm@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , CPU logic power state is never programmed in either the initialization or the suspend/resume logic, instead, we depend on mpuss to program this properly. However, this leaves CPU logic power state indeterminate and most probably in reset configuration (If bootloader or other similar software have'nt monkeyed with the register). This can make powerstate= RET be either programmed for CSWR (logic=ret) or OSWR(logic = OFF) and in OSWR, there can be context loss when the code does not expect it. To prevent all these confusions, just support clearly ON, INA, CSWR, OFF which is the intent of the existing code by explicitly programming logic state. NOTE: since this is a hot path (using in cpuidle), the exit path just programs powerstate (logic state is immaterial when powerstate is ON). Without doing this, we end up with lockups when CPUs enter OSWR and multiple blocks loose context, when we expect them to hit CSWR. Signed-off-by: Nishanth Menon Acked-by: Kevin Hilman --- arch/arm/mach-omap2/omap-mpuss-lowpower.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 6944ae3..79f49d9 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -227,7 +227,7 @@ static void __init save_l2x0_context(void) int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) { struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); - unsigned int save_state = 0; + unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET; unsigned int wakeup_cpu; if (omap_rev() == OMAP4430_REV_ES1_0) @@ -239,6 +239,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) save_state = 0; break; case PWRDM_POWER_OFF: + cpu_logic_state = PWRDM_POWER_OFF; save_state = 1; break; case PWRDM_POWER_RET: @@ -270,6 +271,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) cpu_clear_prev_logic_pwrst(cpu); pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); + pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state); set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume)); omap_pm_ops.scu_prepare(cpu, power_state); l2x0_pwrst_prepare(cpu, save_state);