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[209.132.180.67]) by mx.google.com with ESMTP id b2si11459713pde.9.2014.10.21.07.31.51 for ; Tue, 21 Oct 2014 07:31:54 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933026AbaJUObX (ORCPT + 27 others); Tue, 21 Oct 2014 10:31:23 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:50679 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932875AbaJUObU (ORCPT ); Tue, 21 Oct 2014 10:31:20 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s9LEUuBL028745; Tue, 21 Oct 2014 09:30:56 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9LEUtlV030933; Tue, 21 Oct 2014 09:30:56 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Tue, 21 Oct 2014 09:30:55 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9LEUt6L018459; Tue, 21 Oct 2014 09:30:55 -0500 From: Nishanth Menon To: Tony Lindgren CC: , , , , Nishanth Menon Subject: [PATCH 1/3] ARM: dts: dra72-evm: Provide explicit pinmux for TPS PMIC Date: Tue, 21 Oct 2014 09:30:46 -0500 Message-ID: <1413901848-32268-2-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1413901848-32268-1-git-send-email-nm@ti.com> References: <1413901848-32268-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: nm@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.180 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Even thought sys_nirq1 is hardwired on the SoC for the pin, it is better to configure the pin to the required mux configuration. Signed-off-by: Nishanth Menon --- arch/arm/boot/dts/dra72-evm.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 4107428..671e473 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -26,6 +26,12 @@ 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ >; }; + + tps65917_pins_default: tps65917_pins_default { + pinctrl-single,pins = < + 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ + >; + }; }; &i2c1 { @@ -38,6 +44,9 @@ compatible = "ti,tps65917"; reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&tps65917_pins_default>; + interrupts = ; /* IRQ_SYS_1N */ interrupt-parent = <&gic>; interrupt-controller;