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[209.132.180.67]) by mx.google.com with ESMTP id hj2si14535700pac.169.2014.10.14.19.35.17 for ; Tue, 14 Oct 2014 19:35:18 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932939AbaJOCfO (ORCPT + 27 others); Tue, 14 Oct 2014 22:35:14 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:39420 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932682AbaJOCZr (ORCPT ); Tue, 14 Oct 2014 22:25:47 -0400 Received: from 172.24.2.119 (EHLO szxeml412-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CAT35383; Wed, 15 Oct 2014 10:25:43 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml412-hub.china.huawei.com (10.82.67.91) with Microsoft SMTP Server id 14.3.158.1; Wed, 15 Oct 2014 10:25:32 +0800 From: Yijing Wang To: Bjorn Helgaas CC: , , Xinwei Hu , Wuyun , , Russell King , , , , , Arnd Bergmann , Thomas Gleixner , "Konrad Rzeszutek Wilk" , , Joerg Roedel , , , Benjamin Herrenschmidt , , , Sebastian Ott , "Tony Luck" , , "David S. Miller" , , Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , "Sergei Shtylyov" , Michael Ellerman , Thierry Reding , "Thomas Petazzoni" , Liviu Dudau , Yijing Wang Subject: [PATCH v3 12/27] x86/MSI: Use MSI chip framework to configure MSI/MSI-X irq Date: Wed, 15 Oct 2014 11:07:00 +0800 Message-ID: <1413342435-7876-13-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1413342435-7876-1-git-send-email-wangyijing@huawei.com> References: <1413342435-7876-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: wangyijing@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Use MSI chip framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang --- arch/x86/include/asm/pci.h | 13 +++++++++++++ arch/x86/kernel/apic/io_apic.c | 19 +++++++++++++++++++ arch/x86/pci/acpi.c | 1 + arch/x86/pci/common.c | 3 +++ 4 files changed, 36 insertions(+), 0 deletions(-) diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 0892ea0..f41b58a 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -20,6 +20,9 @@ struct pci_sysdata { #ifdef CONFIG_X86_64 void *iommu; /* IOMMU private data */ #endif +#ifdef CONFIG_PCI_MSI + struct msi_chip *msi_chip; +#endif }; extern int pci_routeirq; @@ -41,6 +44,15 @@ static inline int pci_proc_domain(struct pci_bus *bus) } #endif +#ifdef CONFIG_PCI_MSI +static inline struct msi_chip *pci_msi_chip(struct pci_bus *bus) +{ + struct pci_sysdata *sd = bus->sysdata; + + return sd->msi_chip; +} +#endif + /* Can be used to override the logic in pci_scan_bus for skipping already-configured bus numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the loader */ @@ -101,6 +113,7 @@ void native_teardown_msi_irq(unsigned int irq); void native_restore_msi_irqs(struct pci_dev *dev); int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, unsigned int irq_base, unsigned int irq_offset); +extern struct msi_chip *x86_msi_chip; #else #define native_setup_msi_irqs NULL #define native_teardown_msi_irq NULL diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 29290f5..ec79b38 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -3227,11 +3227,30 @@ int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) return 0; } +static int __native_setup_msi_irqs(struct msi_chip *chip, + struct pci_dev *dev, int nvec, int type) +{ + return native_setup_msi_irqs(dev, nvec, type); +} + void native_teardown_msi_irq(unsigned int irq) { irq_free_hwirq(irq); } +static void __native_teardown_msi_irq(struct msi_chip *chip, + unsigned int irq) +{ + native_teardown_msi_irq(irq); +} + +static struct msi_chip native_msi_chip = { + .setup_irqs = __native_setup_msi_irqs, + .teardown_irq = __native_teardown_msi_irq, +}; + +struct msi_chip *x86_msi_chip = &native_msi_chip; + #ifdef CONFIG_DMAR_TABLE static int dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c index cfd1b13..6341d6d 100644 --- a/arch/x86/pci/acpi.c +++ b/arch/x86/pci/acpi.c @@ -508,6 +508,7 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) sd = &info->sd; sd->domain = domain; + sd->msi_chip = x86_msi_chip; sd->node = node; sd->companion = device; diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 7b20bcc..0b2319a 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -468,6 +468,9 @@ void pcibios_scan_root(int busnum) return; } sd->node = x86_pci_root_bus_node(busnum); +#ifdef CONFIG_PCI_MSI + sd->msi_chip = x86_msi_chip; +#endif x86_pci_root_bus_resources(busnum, &resources); printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum); bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources);