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[90.55.46.235]) by mx.google.com with ESMTPSA id h5sm14014311wje.8.2014.09.28.17.23.58 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 28 Sep 2014 17:23:59 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, mingo@kernel.org Cc: linux-kernel@vger.kernel.org Subject: [PATCH 09/13] clocksource: cadence_ttc: Add support for 32bit mode Date: Mon, 29 Sep 2014 02:23:42 +0200 Message-Id: <1411950226-21598-9-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1411950226-21598-1-git-send-email-daniel.lezcano@linaro.org> References: <5428A559.5050908@linaro.org> <1411950226-21598-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.lezcano@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michal Simek New TTCs support 32bit mode. Older versions support only 16bit modes. Keep 16bit mode as default and 32bit optional. Signed-off-by: Michal Simek Signed-off-by: Daniel Lezcano --- drivers/clocksource/cadence_ttc_timer.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c index 7a08811..510c8a1 100644 --- a/drivers/clocksource/cadence_ttc_timer.c +++ b/drivers/clocksource/cadence_ttc_timer.c @@ -25,7 +25,7 @@ #include /* - * This driver configures the 2 16-bit count-up timers as follows: + * This driver configures the 2 16/32-bit count-up timers as follows: * * T1: Timer 1, clocksource for generic timekeeping * T2: Timer 2, clockevent source for hrtimers @@ -321,7 +321,8 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, return NOTIFY_DONE; } -static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base) +static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base, + u32 timer_width) { struct ttc_timer_clocksource *ttccs; int err; @@ -351,7 +352,7 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base) ttccs->cs.name = "ttc_clocksource"; ttccs->cs.rating = 200; ttccs->cs.read = __ttc_clocksource_read; - ttccs->cs.mask = CLOCKSOURCE_MASK(16); + ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width); ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; /* @@ -372,7 +373,8 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base) } ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET; - sched_clock_register(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE); + sched_clock_register(ttc_sched_clock_read, timer_width, + ttccs->ttc.freq / PRESCALE); } static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, @@ -467,6 +469,7 @@ static void __init ttc_timer_init(struct device_node *timer) struct clk *clk_cs, *clk_ce; static int initialized; int clksel; + u32 timer_width = 16; if (initialized) return; @@ -490,6 +493,8 @@ static void __init ttc_timer_init(struct device_node *timer) BUG(); } + of_property_read_u32(timer, "timer-width", &timer_width); + clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); clk_cs = of_clk_get(timer, clksel); @@ -506,7 +511,7 @@ static void __init ttc_timer_init(struct device_node *timer) BUG(); } - ttc_setup_clocksource(clk_cs, timer_baseaddr); + ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width); ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq); pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);