From patchwork Thu Sep 25 03:14:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: wangyijing X-Patchwork-Id: 37887 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f70.google.com (mail-wg0-f70.google.com [74.125.82.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 472D420063 for ; Thu, 25 Sep 2014 02:51:47 +0000 (UTC) Received: by mail-wg0-f70.google.com with SMTP id a1sf4135428wgh.1 for ; Wed, 24 Sep 2014 19:51:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=n+UDb83sp7ynjV38niIW0cEqCDWT1rTz0UwO+nwxwwE=; b=g1UiuPg9aORsDpw1o2/r0u7K5aKRUboF5JTEzOdoJM7ls1TCk/xke4+B0qQnP1vJpk DcN6hqLDH/axTrV8AmMd/gqU2sXmtvCZ1RL/O2IRXD1mikfVB8RIUMiPdjJeIOKetWEv RioUvvjoaG5Gru3m1A9u0OOA0Kr6CX3qraO6uaCAHDv6rghXy4caLHuM9kR2SFvyTvcN XLy+IW36aPI/p0k8oAhSyM5qmSltK3FtUGk09XJxqqYI7qBHnB0zyn4aXd85MtQWMTHB ysAsRSXMk8GQNsUkJIth5Up3blhbUAqx60WjjNqBMFwGAoO49dj0qapEVTb00hhFz/1w vTOA== X-Gm-Message-State: ALoCoQlpppNC3Tn5i15WYL+R1lBHcrwJRvVlio0Cp2z8hkyOv/57LObIe4d5oxaAsPlmOD7Ev38a X-Received: by 10.180.12.148 with SMTP id y20mr2080796wib.7.1411613506423; Wed, 24 Sep 2014 19:51:46 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.5.169 with SMTP id t9ls228891lat.74.gmail; Wed, 24 Sep 2014 19:51:46 -0700 (PDT) X-Received: by 10.152.45.42 with SMTP id j10mr107801lam.91.1411613506240; Wed, 24 Sep 2014 19:51:46 -0700 (PDT) Received: from mail-la0-f52.google.com (mail-la0-f52.google.com [209.85.215.52]) by mx.google.com with ESMTPS id mn8si1030630lbb.102.2014.09.24.19.51.46 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 24 Sep 2014 19:51:46 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.52 as permitted sender) client-ip=209.85.215.52; Received: by mail-la0-f52.google.com with SMTP id gq15so11825211lab.11 for ; Wed, 24 Sep 2014 19:51:46 -0700 (PDT) X-Received: by 10.152.42.173 with SMTP id p13mr9932902lal.23.1411613506133; Wed, 24 Sep 2014 19:51:46 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.130.169 with SMTP id of9csp683251lbb; Wed, 24 Sep 2014 19:51:45 -0700 (PDT) X-Received: by 10.68.189.137 with SMTP id gi9mr13960471pbc.87.1411613504618; Wed, 24 Sep 2014 19:51:44 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id pl5si1324346pbc.37.2014.09.24.19.51.43 for ; Wed, 24 Sep 2014 19:51:44 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753128AbaIYCvV (ORCPT + 27 others); Wed, 24 Sep 2014 22:51:21 -0400 Received: from szxga01-in.huawei.com ([119.145.14.64]:37209 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752964AbaIYCvJ (ORCPT ); Wed, 24 Sep 2014 22:51:09 -0400 Received: from 172.24.2.119 (EHLO szxeml409-hub.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CCC72766; Thu, 25 Sep 2014 10:50:58 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml409-hub.china.huawei.com (10.82.67.136) with Microsoft SMTP Server id 14.3.158.1; Thu, 25 Sep 2014 10:50:50 +0800 From: Yijing Wang To: Bjorn Helgaas CC: , , Xinwei Hu , Wuyun , , Russell King , , , , , Arnd Bergmann , Thomas Gleixner , "Konrad Rzeszutek Wilk" , , Joerg Roedel , , , Benjamin Herrenschmidt , , , Sebastian Ott , "Tony Luck" , , "David S. Miller" , , Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , "Sergei Shtylyov" , Michael Ellerman , Thierry Reding , "Thomas Petazzoni" , Yijing Wang Subject: [PATCH v2 21/22] tile/MSI: Use MSI chip framework to configure MSI/MSI-X irq Date: Thu, 25 Sep 2014 11:14:31 +0800 Message-ID: <1411614872-4009-22-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: wangyijing@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.52 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Use MSI chip framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang --- arch/tile/kernel/pci_gx.c | 14 ++++++++++++-- 1 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c index e39f9c5..4912b75 100644 --- a/arch/tile/kernel/pci_gx.c +++ b/arch/tile/kernel/pci_gx.c @@ -1485,7 +1485,7 @@ static struct irq_chip tilegx_msi_chip = { /* TBD: support set_affinity. */ }; -int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) +static int tile_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) { struct pci_controller *controller; gxio_trio_context_t *trio_context; @@ -1604,7 +1604,17 @@ is_64_failure: return ret; } -void arch_teardown_msi_irq(unsigned int irq) +void tile_teardown_msi_irq(unsigned int irq) { irq_free_hwirq(irq); } + +static struct msi_chip tile_msi_chip = { + .setup_irq = tile_setup_msi_irq, + .teardown_irq = tile_teardown_msi_irq, +}; + +struct msi_chip *arch_find_msi_chip(struct pci_dev *dev) +{ + return &tile_msi_chip; +}