From patchwork Wed Sep 24 17:17:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 37855 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f200.google.com (mail-wi0-f200.google.com [209.85.212.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 4DF4E204FF for ; Wed, 24 Sep 2014 17:22:46 +0000 (UTC) Received: by mail-wi0-f200.google.com with SMTP id hi2sf3822354wib.7 for ; Wed, 24 Sep 2014 10:22:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=TYwMvj93CcI3fAflMu6X0mD5gUGtNEErSk4R33kgt2I=; b=ej1wV6ZBoDozJl77x9VKlRCEqqvqP2KISIPpsp9RoSgYVItsP6uYQG7IIOiO+gw+Rq BIJa6tt05z0zM65JaestHvXD5Lg8TMboMDyKnrmo+avWWIOsNaFFatXZU6J/D0mFQT8e 36pp7HZwJkXw3NNdtpo2Pjyo+B19wlacuaLWlQHLHnqQr40z1yd6h913JTf9nqZm1fuq 3T+WFVeTvT/xQk/xefz6cNOvWLw7Uy1LrqDJmNMWgkAeETIjyWGhxaWKXmxRMHFxdnOx eGil812jNOqbCZLiRbFqHwJFc1cK814YKsARkknA1INPUeZQd6ZRhdyLgt5D3QCxjlHN GB8w== X-Gm-Message-State: ALoCoQl7xJCG5ZuqPVIYcibCfCAcCnzDBRsS2bsUtM84jMTR/UcqxKhddSALRXXWyYEbEqbWaH1M X-Received: by 10.112.6.138 with SMTP id b10mr602069lba.18.1411579365319; Wed, 24 Sep 2014 10:22:45 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.27.201 with SMTP id v9ls191724lag.40.gmail; Wed, 24 Sep 2014 10:22:45 -0700 (PDT) X-Received: by 10.152.21.168 with SMTP id w8mr7912427lae.59.1411579365122; Wed, 24 Sep 2014 10:22:45 -0700 (PDT) Received: from mail-lb0-f174.google.com (mail-lb0-f174.google.com [209.85.217.174]) by mx.google.com with ESMTPS id r5si23741892lal.3.2014.09.24.10.22.44 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 24 Sep 2014 10:22:44 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) client-ip=209.85.217.174; Received: by mail-lb0-f174.google.com with SMTP id l4so10963670lbv.5 for ; Wed, 24 Sep 2014 10:22:44 -0700 (PDT) X-Received: by 10.112.130.226 with SMTP id oh2mr4273023lbb.100.1411579364688; Wed, 24 Sep 2014 10:22:44 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.130.169 with SMTP id of9csp621380lbb; Wed, 24 Sep 2014 10:22:43 -0700 (PDT) X-Received: by 10.68.220.10 with SMTP id ps10mr10939861pbc.135.1411579363183; Wed, 24 Sep 2014 10:22:43 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id pd5si27304804pbb.28.2014.09.24.10.22.41 for ; Wed, 24 Sep 2014 10:22:43 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754588AbaIXRW2 (ORCPT + 27 others); Wed, 24 Sep 2014 13:22:28 -0400 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:41714 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753953AbaIXRUp (ORCPT ); Wed, 24 Sep 2014 13:20:45 -0400 Received: from edgewater-inn.cambridge.arm.com (edgewater-inn.cambridge.arm.com [10.1.203.204]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id s8OHIqwo025690; Wed, 24 Sep 2014 18:18:52 +0100 (BST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 44ABB1AE11B3; Wed, 24 Sep 2014 18:18:57 +0100 (BST) From: Will Deacon To: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, benh@kernel.crashing.org, chris@zankel.net, cmetcalf@tilera.com, davem@davemloft.net, deller@gmx.de, dhowells@redhat.com, geert@linux-m68k.org, heiko.carstens@de.ibm.com, hpa@zytor.com, jcmvbkbc@gmail.com, jesper.nilsson@axis.com, mingo@redhat.com, monstr@monstr.eu, paulmck@linux.vnet.ibm.com, rdunlap@infradead.org, sam@ravnborg.org, schwidefsky@de.ibm.com, starvik@axis.com, takata@linux-m32r.org, tglx@linutronix.de, tony.luck@intel.com, daniel.thompson@linaro.org, broonie@linaro.org, linux@arm.linux.org.uk, Will Deacon Subject: [PATCH v3 06/17] cris: io: implement dummy relaxed accessor macros for writes Date: Wed, 24 Sep 2014 18:17:25 +0100 Message-Id: <1411579056-16966-7-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1411579056-16966-1-git-send-email-will.deacon@arm.com> References: <1411579056-16966-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: will.deacon@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , write{b,w,l}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to Cris, in the same vein as the dummy definitions for the relaxed read accessors. Cc: Mikael Starvik Acked-by: Jesper Nilsson Signed-off-by: Will Deacon --- arch/cris/include/asm/io.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/cris/include/asm/io.h b/arch/cris/include/asm/io.h index e59dba12ce94..752a3f45df60 100644 --- a/arch/cris/include/asm/io.h +++ b/arch/cris/include/asm/io.h @@ -112,6 +112,9 @@ static inline void writel(unsigned int b, volatile void __iomem *addr) else *(volatile unsigned int __force *) addr = b; } +#define writeb_relaxed(b, addr) writeb(b, addr) +#define writew_relaxed(b, addr) writew(b, addr) +#define writel_relaxed(b, addr) writel(b, addr) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel