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[209.132.180.67]) by mx.google.com with ESMTP id fk2si41012061pdb.228.2014.09.18.12.05.51 for ; Thu, 18 Sep 2014 12:05:52 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756574AbaIRTFp (ORCPT + 27 others); Thu, 18 Sep 2014 15:05:45 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:40102 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756485AbaIRTFn (ORCPT ); Thu, 18 Sep 2014 15:05:43 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s8IJ4ndr012276; Thu, 18 Sep 2014 14:04:49 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s8IJ4mDd016721; Thu, 18 Sep 2014 14:04:49 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Thu, 18 Sep 2014 14:04:48 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s8IJ4mqA017797; Thu, 18 Sep 2014 14:04:48 -0500 From: Nishanth Menon To: CC: Thomas Gleixner , , , Keerthy , Mark Brown , Samuel Ortiz , , Tony Lindgren , , Nishanth Menon Subject: [PATCH V3 2/3] Documentation: dt-bindings: mfd: palmas: document optional wakeup IRQ Date: Thu, 18 Sep 2014 14:04:45 -0500 Message-ID: <1411067086-16613-3-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1411067086-16613-1-git-send-email-nm@ti.com> References: <1411067086-16613-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: nm@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , With the recent pinctrl-single changes, SoCs such as OMAP family can treat wake-up events from deeper low power states as interrupts. This is usable when the wakeup from deeper low power states is triggered by a different hardware mechanism tied to pinctrl compared to the routine interrupt handling generating the reqular interrupt events. This is usually done on SoCs where the routine interrupt sources such as GPIO need to be disabled to be actually achieve low power state and wakeup is triggered from pinctrl interrupt source. Provide documentation example for the case where the system needs two interrupt sources when SoC is in deep sleep(1 to exit from deep sleep, and other from the module handling the actual event). Signed-off-by: Nishanth Menon --- V3: no change V2: http://marc.info/?l=linux-kernel&m=140995036418561&w=2 Documentation/devicetree/bindings/mfd/palmas.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt index d193859..1c821d6 100644 --- a/Documentation/devicetree/bindings/mfd/palmas.txt +++ b/Documentation/devicetree/bindings/mfd/palmas.txt @@ -51,3 +51,23 @@ palmas@48 { .... }; } + +Example: With interrupts extended + See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + Use pinmux 0x418 as wakeup interrupt and gpio1_0 as interrupt source + +palmas@48 { + compatible = "ti,twl6035", "ti,palmas"; + reg = <0x48> + interrupt-parent = <&intc>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + interrupts-extended = <&gpio1 0 IRQ_TYPE_LEVEL_HIGH>, + <&pinmux 0x418>; + pmic { + compatible = "ti,twl6035-pmic", "ti,palmas-pmic"; + .... + }; +}