From patchwork Thu Sep 4 16:03:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 36732 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f71.google.com (mail-pa0-f71.google.com [209.85.220.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id DC435202E4 for ; Thu, 4 Sep 2014 16:04:09 +0000 (UTC) Received: by mail-pa0-f71.google.com with SMTP id et14sf94523894pad.6 for ; Thu, 04 Sep 2014 09:04:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=TYYZ14wGpAAladcev26NIFS6juHLTJJHYp7zHdvQiZ0=; b=D/enqwMo9NB7uTX7K1dc/7VEfCrvmxNreOa5VH5lWmbzRsL+bNpTImlqEajY8WLARX Nb8dgsNzoKZnGFIpgtAG4QxmObI3kOdINi4f+s1OI+03L5pZ+ceK0rz7heoBsiC3sB8C 1YFN/Wi6+KymwT7NuLZIPknc/gurEdOPLQmQLxy8jAZpgPDkZAs/B5aIvyM04KcY2hvX 8Ea5ze40VDiBgFWmkXhyj1dwiCb0QgvUsDnAxA1k+qgDPG3gJJTRjAcuJ+kfaQW/hZuW 67qmKLOSgRidUrf0mZENVgrMGwyM3Yg7EyW1t/HAZ/l02omtSBAoflZ7QY53/OwgSVKJ iO+w== X-Gm-Message-State: ALoCoQl5C08rJMy/Th60Mf84LR0cLDPl+dd8tPXa53m58yCW1g3B5eAOnRmlu0C7WTHyzXho2/JT X-Received: by 10.66.147.227 with SMTP id tn3mr3034207pab.4.1409846646861; Thu, 04 Sep 2014 09:04:06 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.51.170 with SMTP id u39ls349301qga.21.gmail; Thu, 04 Sep 2014 09:04:06 -0700 (PDT) X-Received: by 10.52.168.134 with SMTP id zw6mr4158411vdb.37.1409846646706; Thu, 04 Sep 2014 09:04:06 -0700 (PDT) Received: from mail-vc0-f169.google.com (mail-vc0-f169.google.com [209.85.220.169]) by mx.google.com with ESMTPS id uy8si5988760vcb.72.2014.09.04.09.04.06 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 04 Sep 2014 09:04:06 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.169 as permitted sender) client-ip=209.85.220.169; Received: by mail-vc0-f169.google.com with SMTP id hq11so11041584vcb.0 for ; Thu, 04 Sep 2014 09:04:06 -0700 (PDT) X-Received: by 10.52.3.40 with SMTP id 8mr4242424vdz.24.1409846646628; Thu, 04 Sep 2014 09:04:06 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.45.67 with SMTP id uj3csp861277vcb; Thu, 4 Sep 2014 09:04:06 -0700 (PDT) X-Received: by 10.194.75.138 with SMTP id c10mr7365659wjw.9.1409846645454; Thu, 04 Sep 2014 09:04:05 -0700 (PDT) Received: from mail-wg0-f44.google.com (mail-wg0-f44.google.com [74.125.82.44]) by mx.google.com with ESMTPS id j6si17288123wjn.116.2014.09.04.09.04.05 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 04 Sep 2014 09:04:05 -0700 (PDT) Received-SPF: pass (google.com: domain of daniel.thompson@linaro.org designates 74.125.82.44 as permitted sender) client-ip=74.125.82.44; Received: by mail-wg0-f44.google.com with SMTP id m15so10337079wgh.15 for ; Thu, 04 Sep 2014 09:04:05 -0700 (PDT) X-Received: by 10.194.78.170 with SMTP id c10mr7421124wjx.22.1409846644870; Thu, 04 Sep 2014 09:04:04 -0700 (PDT) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id m9sm19841199wjz.35.2014.09.04.09.04.03 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Sep 2014 09:04:04 -0700 (PDT) From: Daniel Thompson To: Russell King Cc: Daniel Thompson , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patches@linaro.org, linaro-kernel@lists.linaro.org, John Stultz , Thomas Gleixner , Sumit Semwal , Jason Cooper Subject: [PATCH v1 5/6] irqchip: gic: Group 0 workaround. Date: Thu, 4 Sep 2014 17:03:39 +0100 Message-Id: <1409846620-14542-6-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1409846620-14542-1-git-send-email-daniel.thompson@linaro.org> References: <1409662853-29313-1-git-send-email-daniel.thompson@linaro.org> <1409846620-14542-1-git-send-email-daniel.thompson@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.thompson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , An ARM system based on GICv1 that runs by default in secure mode and uses both group 0 and group 1 interrupts (in order to exploit FIQ) will suffer a problem where the IRQ handler occasionally spuriously acknowledges a group 0 (FIQ) interrupt. This can be prevented by ensuring the IRQ handler makes non-secure memory access to the GIC registers but this is complex because the non-secure bits cannot be apply to 4k pages (the bit is one level up in the page table and applies to 1MB at a time). This workaround uses an alternative approach that spots the spurious acknowledgment and regenerates the FIQ. This keeps the workaround exclusively within the GIC driver (although there is a runtime perforamnce penalty resulting from this approach). Reported-by: Harro Haan Signed-off-by: Daniel Thompson Tested-by: Harro Haan Cc: Thomas Gleixner Cc: Jason Cooper --- drivers/irqchip/irq-gic.c | 52 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index ffc64ed..4b25ed9 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -267,14 +267,59 @@ static int gic_set_wake(struct irq_data *d, unsigned int on) #define gic_set_wake NULL #endif +#ifdef CONFIG_FIQ +/* This is a software emulation of the Aliased Interrupt Acknowledge Register + * (GIC_AIAR) found in GICv2+. + */ +static u32 gic_handle_spurious_group_0(struct gic_chip_data *gic, u32 irqstat) +{ + u32 irqnr = irqstat & GICC_IAR_INT_ID_MASK; + void __iomem *dist_base = gic_data_dist_base(gic); + u32 offset, mask; + + if (readl_relaxed(dist_base + GIC_DIST_IGROUP + 0) || irqnr >= 1021) + return irqstat; + + offset = irqnr / 32 * 4; + mask = 1 << (irqnr % 32); + if (readl_relaxed(dist_base + GIC_DIST_IGROUP + offset) & mask) + return irqstat; + + /* this interrupt must be taken as a FIQ so put it back into the + * pending state and end our own servicing of it. + */ + writel_relaxed(mask, dist_base + GIC_DIST_PENDING_SET + offset); + readl_relaxed(dist_base + GIC_DIST_PENDING_SET + offset); + writel_relaxed(irqstat, gic_data_cpu_base(gic) + GIC_CPU_EOI); + + return 1023; +} + +static u32 gic_ack_irq(struct gic_chip_data *gic) +{ + u32 irqstat; + + local_fiq_disable(); + irqstat = readl_relaxed(gic_data_cpu_base(gic) + GIC_CPU_INTACK); + irqstat = gic_handle_spurious_group_0(gic, irqstat); + local_fiq_enable(); + + return irqstat; +} +#else +static u32 gic_ack_irq(struct gic_chip_data *gic) +{ + return readl_relaxed(gic_data_cpu_base(gic) + GIC_CPU_INTACK); +} +#endif + static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) { u32 irqstat, irqnr; struct gic_chip_data *gic = &gic_data[0]; - void __iomem *cpu_base = gic_data_cpu_base(gic); do { - irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); + irqstat = gic_ack_irq(gic); irqnr = irqstat & GICC_IAR_INT_ID_MASK; if (likely(irqnr > 15 && irqnr < 1021)) { @@ -283,7 +328,8 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) continue; } if (irqnr < 16) { - writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); + writel_relaxed(irqstat, + gic_data_cpu_base(gic) + GIC_CPU_EOI); #ifdef CONFIG_SMP handle_IPI(irqnr, regs); #endif