From patchwork Tue Aug 19 16:45:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 35633 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qc0-f197.google.com (mail-qc0-f197.google.com [209.85.216.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id CF12F202DD for ; Tue, 19 Aug 2014 16:50:50 +0000 (UTC) Received: by mail-qc0-f197.google.com with SMTP id c9sf20894497qcz.0 for ; Tue, 19 Aug 2014 09:50:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=nzk2D8NwDPR8us2X6gDWosD4X78vVgNIn9azhM6mFHk=; b=UtYZyyZ7Rov2yVJyRYgnzhzwxKYT1NWr6bYBct7LGRcOfBUwbdRr0QXNHHClbUSd64 Ok9ibcYtQ+iy+yHYw/hGuNYgWaZsQRmxafs/eHv8Eomu58Q7XWhJS/DwXDk5qJfrxYbC 8VzZIHvdzTQLWEODH2r3Htwo9IYiCfLHe1gDg8HQC5nXuvdg4wpUXgy1VDk9oOQQwXVg GEX9mZUzaH6a32OkdmVDogfyJdHNgDmoCClXN42Cc51SQKQpOjVDwAgtt5KUOucxcZ2s ojYEfHxCRlny9Q2GlHhw3nF/OaB07vL1rFD2nRso/qQtWSGJBiDBrcPJjZa9LNpADT5A yKBA== X-Gm-Message-State: ALoCoQmD+twOsb1oOlbSEw89mo8FnSgDvaLHUUuGNzGEf/kaHz0KblwW9Tor5kZOml7YAOjUOk4/ X-Received: by 10.236.63.197 with SMTP id a45mr21304607yhd.9.1408467045200; Tue, 19 Aug 2014 09:50:45 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.41.11 with SMTP id y11ls2894447qgy.23.gmail; Tue, 19 Aug 2014 09:50:45 -0700 (PDT) X-Received: by 10.220.172.134 with SMTP id l6mr643968vcz.80.1408467045140; Tue, 19 Aug 2014 09:50:45 -0700 (PDT) Received: from mail-vc0-f174.google.com (mail-vc0-f174.google.com [209.85.220.174]) by mx.google.com with ESMTPS id fb5si9131444vdc.12.2014.08.19.09.50.45 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 19 Aug 2014 09:50:45 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) client-ip=209.85.220.174; Received: by mail-vc0-f174.google.com with SMTP id la4so7625921vcb.5 for ; Tue, 19 Aug 2014 09:50:45 -0700 (PDT) X-Received: by 10.52.120.51 with SMTP id kz19mr551361vdb.95.1408467045070; Tue, 19 Aug 2014 09:50:45 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp254638vcb; Tue, 19 Aug 2014 09:50:44 -0700 (PDT) X-Received: by 10.180.187.20 with SMTP id fo20mr792848wic.58.1408467043909; Tue, 19 Aug 2014 09:50:43 -0700 (PDT) Received: from mail-we0-f182.google.com (mail-we0-f182.google.com [74.125.82.182]) by mx.google.com with ESMTPS id fo10si23297308wib.77.2014.08.19.09.50.43 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 19 Aug 2014 09:50:43 -0700 (PDT) Received-SPF: pass (google.com: domain of daniel.thompson@linaro.org designates 74.125.82.182 as permitted sender) client-ip=74.125.82.182; Received: by mail-we0-f182.google.com with SMTP id k48so6791471wev.27 for ; Tue, 19 Aug 2014 09:50:43 -0700 (PDT) X-Received: by 10.194.75.138 with SMTP id c10mr46499408wjw.9.1408467043507; Tue, 19 Aug 2014 09:50:43 -0700 (PDT) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id gc8sm36225wic.3.2014.08.19.09.50.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Aug 2014 09:50:42 -0700 (PDT) From: Daniel Thompson To: Russell King Cc: Daniel Thompson , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kgdb-bugreport@lists.sourceforge.net, patches@linaro.org, linaro-kernel@lists.linaro.org, John Stultz , Anton Vorontsov , Colin Cross , kernel-team@android.com, Rob Herring , Linus Walleij , Ben Dooks , Catalin Marinas , Dave Martin , Fabio Estevam , Frederic Weisbecker , Nicolas Pitre , Thomas Gleixner , Jason Cooper , Nicolas Pitre , Christoffer Dall , Sricharan R Subject: [PATCH v10 07/19] irqchip: gic: Add support for FIQ management Date: Tue, 19 Aug 2014 17:45:57 +0100 Message-Id: <1408466769-20004-8-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1408466769-20004-1-git-send-email-daniel.thompson@linaro.org> References: <1408369264-14242-1-git-send-email-daniel.thompson@linaro.org> <1408466769-20004-1-git-send-email-daniel.thompson@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.thompson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch introduces callbacks to route interrupts to or away from the FIQ signal and registers these callbacks with the FIQ infrastructure (if the device can supports it). Both these aspects combine and allow a driver to deploy a FIQ handler without any machine specific knowledge; it can be used effectively on multi-platform kernels. Signed-off-by: Daniel Thompson Cc: Thomas Gleixner Cc: Jason Cooper Cc: Nicolas Pitre Cc: Christoffer Dall Cc: Sricharan R --- drivers/irqchip/irq-gic.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 423707c..6fa0542 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -342,6 +342,69 @@ static struct irq_chip gic_chip = { }; #ifdef CONFIG_FIQ +/* + * Shift an interrupt between Group 0 and Group 1. + * + * In addition to changing the group we also modify the priority to + * match what "ARM strongly recommends" for a system where no Group 1 + * interrupt must ever preempt a Group 0 interrupt. + */ +static void gic_set_group_irq(struct irq_data *d, int group) +{ + unsigned int grp_reg = gic_irq(d) / 32 * 4; + u32 grp_mask = 1 << (gic_irq(d) % 32); + u32 grp_val; + + unsigned int pri_reg = (gic_irq(d) / 4) * 4; + u32 pri_mask = 1 << (7 + ((gic_irq(d) % 4) * 8)); + u32 pri_val; + + raw_spin_lock(&irq_controller_lock); + + grp_val = readl_relaxed(gic_dist_base(d) + GIC_DIST_IGROUP + grp_reg); + pri_val = readl_relaxed(gic_dist_base(d) + GIC_DIST_PRI + pri_reg); + + if (group) { + grp_val |= grp_mask; + pri_val |= pri_mask; + } else { + grp_val &= ~grp_mask; + pri_val &= ~pri_mask; + } + + writel_relaxed(grp_val, gic_dist_base(d) + GIC_DIST_IGROUP + grp_reg); + writel_relaxed(pri_val, gic_dist_base(d) + GIC_DIST_PRI + pri_reg); + + raw_spin_unlock(&irq_controller_lock); +} + +static void gic_enable_fiq(struct irq_data *d) +{ + gic_set_group_irq(d, 0); +} + +static void gic_disable_fiq(struct irq_data *d) +{ + gic_set_group_irq(d, 1); +} + +static int gic_ack_fiq(struct irq_data *d) +{ + struct gic_chip_data *gic = irq_data_get_irq_chip_data(d); + u32 irqstat, irqnr; + + irqstat = readl_relaxed(gic_data_cpu_base(gic) + GIC_CPU_INTACK); + irqnr = irqstat & GICC_IAR_INT_ID_MASK; + return irq_find_mapping(gic->domain, irqnr); +} + +static struct fiq_chip gic_fiq = { + .fiq_enable = gic_enable_fiq, + .fiq_disable = gic_disable_fiq, + .fiq_ack = gic_ack_fiq, + .fiq_eoi = gic_eoi_irq, +}; + static void __init gic_init_fiq(struct gic_chip_data *gic, irq_hw_number_t first_irq, unsigned int num_irqs) @@ -370,6 +433,12 @@ static void __init gic_init_fiq(struct gic_chip_data *gic, if (!gic->fiq_enable) return; + + /* + * FIQ is supported on this device! Register our chip data. + */ + for (i = 0; i < num_irqs; i++) + fiq_register_mapping(first_irq + i, &gic_fiq); } #else /* CONFIG_FIQ */ static inline void gic_init_fiq(struct gic_chip_data *gic,