From patchwork Thu Aug 14 11:15:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 35397 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ob0-f197.google.com (mail-ob0-f197.google.com [209.85.214.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 693CA203C5 for ; Thu, 14 Aug 2014 11:16:05 +0000 (UTC) Received: by mail-ob0-f197.google.com with SMTP id vb8sf6137527obc.4 for ; Thu, 14 Aug 2014 04:16:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=nCZvo5bUTIp3zrioIuhiRCsTkYW2lIduGkFQ7dixIKE=; b=Ap2puUmVTvqtd7Yn0Q2aWDAqU+RV3bSNODBUZK3KR0CPDjgqgndmKQkaHgnBy4qFer CrChtBnDsVdwXi6sf5rSIM28azbvK415FkZovqRNonc7YeXHrrOoJtAJClz8WV3VEdQH smJlPpWtQTc0DgMexgKdL5zduacApfOftKUSZEq+DGIfpgjdgNlq7rfgLLcQHRn4RnLU 7sQEOE5K5zT12RvprDRPTMSXI+Voef7k4RlszKYQLcOYwYlBCujMuWxWDpfxYmewo3+n 40egZqS7NKFAreRkTiRc54Uo5nSgN/pyeHJndyXSHwwNXXfLEU5WJWWJTrdkNhjXx8tF Wtng== X-Gm-Message-State: ALoCoQl7OO+ap+2rcaP+Wfjj26IDVxEzD0PRQpjvsQrfBssdVUEx2tn3V2+S7V+5Tdcyl35hPG1q X-Received: by 10.50.138.167 with SMTP id qr7mr6141796igb.6.1408014965053; Thu, 14 Aug 2014 04:16:05 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.23.137 with SMTP id 9ls913070qgp.68.gmail; Thu, 14 Aug 2014 04:16:05 -0700 (PDT) X-Received: by 10.52.150.17 with SMTP id ue17mr38934vdb.89.1408014964971; Thu, 14 Aug 2014 04:16:04 -0700 (PDT) Received: from mail-vc0-f171.google.com (mail-vc0-f171.google.com [209.85.220.171]) by mx.google.com with ESMTPS id y2si795190ved.77.2014.08.14.04.16.04 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 14 Aug 2014 04:16:04 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.171 as permitted sender) client-ip=209.85.220.171; Received: by mail-vc0-f171.google.com with SMTP id hq11so1172683vcb.2 for ; Thu, 14 Aug 2014 04:16:04 -0700 (PDT) X-Received: by 10.221.5.137 with SMTP id og9mr3077431vcb.18.1408014964863; Thu, 14 Aug 2014 04:16:04 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp25095vcb; Thu, 14 Aug 2014 04:16:04 -0700 (PDT) X-Received: by 10.194.200.74 with SMTP id jq10mr3012891wjc.110.1408014963602; Thu, 14 Aug 2014 04:16:03 -0700 (PDT) Received: from mail-wi0-f178.google.com (mail-wi0-f178.google.com [209.85.212.178]) by mx.google.com with ESMTPS id z1si29709431wiw.106.2014.08.14.04.16.03 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 14 Aug 2014 04:16:03 -0700 (PDT) Received-SPF: pass (google.com: domain of daniel.thompson@linaro.org designates 209.85.212.178 as permitted sender) client-ip=209.85.212.178; Received: by mail-wi0-f178.google.com with SMTP id hi2so2111518wib.17 for ; Thu, 14 Aug 2014 04:16:02 -0700 (PDT) X-Received: by 10.180.221.172 with SMTP id qf12mr11260003wic.18.1408014962613; Thu, 14 Aug 2014 04:16:02 -0700 (PDT) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id gb5sm18966593wib.8.2014.08.14.04.16.00 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Aug 2014 04:16:01 -0700 (PDT) From: Daniel Thompson To: Russell King Cc: Daniel Thompson , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kgdb-bugreport@lists.sourceforge.net, patches@linaro.org, linaro-kernel@lists.linaro.org, John Stultz , Anton Vorontsov , Colin Cross , kernel-team@android.com, Rob Herring , Linus Walleij , Ben Dooks , Catalin Marinas , Dave Martin , Fabio Estevam , Frederic Weisbecker , Nicolas Pitre Subject: [RFC PATCH 1/3] arm: smp: Introduce a special IPI signalled using FIQ Date: Thu, 14 Aug 2014 12:15:49 +0100 Message-Id: <1408014951-24820-2-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1408014951-24820-1-git-send-email-daniel.thompson@linaro.org> References: <53EC9404.5010908@linaro.org> <1408014951-24820-1-git-send-email-daniel.thompson@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.thompson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Cross CPU signalling based on FIQ is especially useful for kgdb since it makes stopping all the CPUs during breakpointing more robust (some of the other architectures already roundup the CPUs using NMIs). The approach taken provides infrastructure that can be called (or not) by the driver's FIQ handler depending upon it requirements. In other words nothing is added here that prevents the driver from accessing "bare metal" performance. Signed-off-by: Daniel Thompson --- arch/arm/include/asm/hardirq.h | 2 +- arch/arm/include/asm/smp.h | 11 +++++++++++ arch/arm/kernel/smp.c | 44 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h index fe3ea77..5df33e3 100644 --- a/arch/arm/include/asm/hardirq.h +++ b/arch/arm/include/asm/hardirq.h @@ -5,7 +5,7 @@ #include #include -#define NR_IPI 8 +#define NR_IPI 9 typedef struct { unsigned int __softirq_pending; diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 2ec765c..6a969f8 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -20,6 +20,9 @@ #define raw_smp_processor_id() (current_thread_info()->cpu) +/* bitmap of IPIs that must be signalled using FIQ */ +#define SMP_IPI_FIQ_MASK 0x0100 + struct seq_file; /* @@ -87,6 +90,14 @@ extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask); extern int register_ipi_completion(struct completion *completion, int cpu); +#ifdef CONFIG_FIQ +extern void send_fiq_ipi_mask(const struct cpumask *); +extern int __init register_fiq_ipi_notifier(struct notifier_block *nb); +void handle_IPI_FIQ(struct pt_regs *regs); +#else +#define register_fiq_ipi_notifier(nb) +#endif + struct smp_operations { #ifdef CONFIG_SMP /* diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 9388a3d..71557bc 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -72,6 +72,7 @@ enum ipi_msg_type { IPI_CPU_STOP, IPI_IRQ_WORK, IPI_COMPLETION, + IPI_FIQ, }; static DECLARE_COMPLETION(cpu_running); @@ -451,6 +452,7 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = { S(IPI_CPU_STOP, "CPU stop interrupts"), S(IPI_IRQ_WORK, "IRQ work interrupts"), S(IPI_COMPLETION, "completion interrupts"), + S(IPI_FIQ, "FIQ interrupts"), }; static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) @@ -552,6 +554,42 @@ static void ipi_complete(unsigned int cpu) complete(per_cpu(cpu_completion, cpu)); } +#ifdef CONFIG_FIQ +static ATOMIC_NOTIFIER_HEAD(fiq_ipi_chain); + +/* + * Caller must ensure a FIQ handler that can clear the IPI is installed + * before calling this function. This is normally achieved by calling + * handle_IPI_FIQ() from the FIQ handler. + */ +void send_fiq_ipi_mask(const struct cpumask *mask) +{ + smp_cross_call(mask, IPI_FIQ); +} + +int __init register_fiq_ipi_notifier(struct notifier_block *nb) +{ + return atomic_notifier_chain_register(&fiq_ipi_chain, nb); +} + +void handle_IPI_FIQ(struct pt_regs *regs) +{ + unsigned int cpu = smp_processor_id(); + struct pt_regs *old_regs = set_irq_regs(regs); + + /* Make sure the FIQ mask matches our assumptions */ + BUILD_BUG_ON(SMP_IPI_FIQ_MASK ^ (1 << IPI_FIQ)); + + __inc_irq_stat(cpu, ipi_irqs[IPI_FIQ]); + + nmi_enter(); + atomic_notifier_call_chain(&fiq_ipi_chain, IPI_FIQ, NULL); + nmi_exit(); + + set_irq_regs(old_regs); +} +#endif + /* * Main handler for inter-processor interrupts */ @@ -618,6 +656,12 @@ void handle_IPI(int ipinr, struct pt_regs *regs) irq_exit(); break; +#ifdef CONFIG_FIQ + case IPI_FIQ: + pr_crit("CPU%u: IPI FIQ delivered via IRQ vector\n", cpu); + break; +#endif + default: printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);