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[67.197.104.99]) by mx.google.com with ESMTPSA id oy12sm6901839pbb.27.2014.07.24.17.52.05 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Jul 2014 17:52:06 -0700 (PDT) From: Matt Turner To: Linus Torvalds Cc: linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, Will Deacon , Ivan Kokshaysky , Matt Turner Subject: [PATCH 2/2] alpha: io: implement relaxed accessor macros for writes Date: Thu, 24 Jul 2014 17:53:54 -0700 Message-Id: <1406249634-27136-2-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.8.5.5 In-Reply-To: <1406249634-27136-1-git-send-email-mattst88@gmail.com> References: <1406249634-27136-1-git-send-email-mattst88@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Original-Sender: mattst88@gmail.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c03::22b as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=neutral (body hash did not verify) header.i=@; dmarc=fail (p=NONE dis=NONE) header.from=gmail.com Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Will Deacon write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O writes with weaker barrier semantics than the non-relaxed variants. This patch implements these write macros for Alpha, in the same vein as the relaxed read macros, which are already implemented. Acked-by: Richard Henderson Cc: Ivan Kokshaysky Signed-off-by: Will Deacon Signed-off-by: Matt Turner --- arch/alpha/include/asm/io.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/alpha/include/asm/io.h b/arch/alpha/include/asm/io.h index 5ebab58..f05bdb4 100644 --- a/arch/alpha/include/asm/io.h +++ b/arch/alpha/include/asm/io.h @@ -500,10 +500,14 @@ extern inline void writeq(u64 b, volatile void __iomem *addr) #define outb_p outb #define outw_p outw #define outl_p outl -#define readb_relaxed(addr) __raw_readb(addr) -#define readw_relaxed(addr) __raw_readw(addr) -#define readl_relaxed(addr) __raw_readl(addr) -#define readq_relaxed(addr) __raw_readq(addr) +#define readb_relaxed(addr) __raw_readb(addr) +#define readw_relaxed(addr) __raw_readw(addr) +#define readl_relaxed(addr) __raw_readl(addr) +#define readq_relaxed(addr) __raw_readq(addr) +#define writeb_relaxed(b, addr) __raw_writeb(b, addr) +#define writew_relaxed(b, addr) __raw_writew(b, addr) +#define writel_relaxed(b, addr) __raw_writel(b, addr) +#define writeq_relaxed(b, addr) __raw_writeq(b, addr) #define mmiowb()