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[82.33.25.158]) by mx.google.com with ESMTPSA id di7sm38135166wjb.34.2014.07.21.07.48.13 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Jul 2014 07:48:14 -0700 (PDT) From: Daniel Thompson To: Russell King , Thomas Gleixner , Jason Cooper Cc: Daniel Thompson , Marex Vasut , Harro Haan , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patches@linaro.org, linaro-kernel@lists.linaro.org, John Stultz , Peter De Schrijver Subject: [PATCH RFC 3/9] irqchip: gic: Remove spin locks from eoi_irq Date: Mon, 21 Jul 2014 15:47:14 +0100 Message-Id: <1405954040-30399-4-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1405954040-30399-1-git-send-email-daniel.thompson@linaro.org> References: <1405954040-30399-1-git-send-email-daniel.thompson@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.thompson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.180 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch is motivated by the comment it removes from gic_init_fiq, namely that the spin locks in eoi_irq preclude certain platforms from supporting FIQ. Currently there is only one upstream platform (tegra) that actually hooks gic_arch_extn.irq_eoi and it does not require these spin locks. Signed-off-by: Daniel Thompson Cc: Thomas Gleixner Cc: Jason Cooper Cc: Peter De Schrijver --- drivers/irqchip/irq-gic.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index d3c7559..5c934a4 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -191,11 +191,8 @@ static void gic_unmask_irq(struct irq_data *d) static void gic_eoi_irq(struct irq_data *d) { - if (gic_arch_extn.irq_eoi) { - raw_spin_lock(&irq_controller_lock); + if (gic_arch_extn.irq_eoi) gic_arch_extn.irq_eoi(d); - raw_spin_unlock(&irq_controller_lock); - } writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); } @@ -437,13 +434,6 @@ static void __init gic_init_fiq(struct gic_chip_data *gic, unsigned int i; /* - * FIQ can only be supported on platforms without an extended irq_eoi - * method (otherwise we take a lock during eoi handling). - */ - if (gic_arch_extn.irq_eoi) - return; - - /* * If grouping is not available (not implemented or prohibited by * security mode) these registers a read-as-zero/write-ignored. * However as a precaution we restore the reset default regardless of