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[2.99.226.247]) by mx.google.com with ESMTPSA id eh10sm6227810wic.0.2014.07.16.01.18.57 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 16 Jul 2014 01:18:57 -0700 (PDT) From: Srinivas Kandagatla To: Kishon Vijay Abraham I Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-ide@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH] phy: qcom-apq8064: fix possible timeout without check Date: Wed, 16 Jul 2014 09:18:43 +0100 Message-Id: <1405498723-10681-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: srinivas.kandagatla@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch fixes a possible timeout in poll loop without actually checking the register before return. In theory the there is a possibility of loop being scheduled after a long lock/delay, which would then force the loop to exit without actually checking the register. Reported-by: Bartlomiej Zolnierkiewicz Signed-off-by: Srinivas Kandagatla --- Hi Kishon, Just to make it easy for you, am sending this change as a seperate patch so that you can apply it on top of linux-phy next. Thanks, srini drivers/phy/phy-qcom-apq8064-sata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/phy-qcom-apq8064-sata.c b/drivers/phy/phy-qcom-apq8064-sata.c index c9b4dd6..f91e254 100644 --- a/drivers/phy/phy-qcom-apq8064-sata.c +++ b/drivers/phy/phy-qcom-apq8064-sata.c @@ -91,7 +91,7 @@ static int read_poll_timeout(void __iomem *addr, u32 mask) usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50); } while (!time_after(jiffies, timeout)); - return -ETIMEDOUT; + return (readl_relaxed(addr) & mask) ? 0 : -ETIMEDOUT; } static int qcom_apq8064_sata_phy_init(struct phy *generic_phy)