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[209.132.180.67]) by mx.google.com with ESMTP id rl10si8853064pbc.161.2014.07.14.03.43.40; Mon, 14 Jul 2014 03:43:40 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754518AbaGNKng (ORCPT + 28 others); Mon, 14 Jul 2014 06:43:36 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:39069 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754468AbaGNKn2 (ORCPT ); Mon, 14 Jul 2014 06:43:28 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6EAh4cG012687; Mon, 14 Jul 2014 05:43:04 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6EAh4Yb023118; Mon, 14 Jul 2014 05:43:04 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Mon, 14 Jul 2014 05:43:04 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6EAgdF1003492; Mon, 14 Jul 2014 05:43:01 -0500 From: Kishon Vijay Abraham I To: , , , , CC: , Rob Herring , Pawel Moll , Mark Rutland , Kumar Gala Subject: [RESEND PATCH 6/8] ARM: dts: dra7: Add dt data for PCIe PHY control module Date: Mon, 14 Jul 2014 16:12:21 +0530 Message-ID: <1405334543-25509-7-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1405334543-25509-1-git-send-email-kishon@ti.com> References: <1405334543-25509-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: kishon@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Added dt data for PCIe PHY control module used by PCIe PHY. The documention for this node can be found @ ../bindings/phy/ti-phy.txt Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 961be6b..e4999e4 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -828,6 +828,23 @@ ti,hwmods = "sata"; }; + omap_control_pcie1phy: control-phy@0x4a003c40 { + compatible = "ti,control-phy-pcie"; + reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; + reg-names = "power", "control_sma", "pcie_pcs"; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + }; + + omap_control_pcie2phy: control-pcie@0x4a003c44 { + compatible = "ti,control-phy-pcie"; + reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; + reg-names = "power", "control_sma", "pcie_pcs"; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + status = "disabled"; + }; + omap_control_usb2phy1: control-phy@4a002300 { compatible = "ti,control-phy-usb2"; reg = <0x4a002300 0x4>;