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[209.132.180.67]) by mx.google.com with ESMTP id km8si1909315pbc.28.2014.07.14.03.43.19; Mon, 14 Jul 2014 03:43:19 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754322AbaGNKnQ (ORCPT + 6 others); Mon, 14 Jul 2014 06:43:16 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:39051 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751411AbaGNKnI (ORCPT ); Mon, 14 Jul 2014 06:43:08 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6EAgjJC012663; Mon, 14 Jul 2014 05:42:45 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6EAgjgb022833; Mon, 14 Jul 2014 05:42:45 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Mon, 14 Jul 2014 05:42:45 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6EAgdEu003492; Mon, 14 Jul 2014 05:42:42 -0500 From: Kishon Vijay Abraham I To: , , , , CC: , Keerthy , Rajendra Nayak , Tero Kristo , Paul Walmsley Subject: [RESEND PATCH 1/8] ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock Date: Mon, 14 Jul 2014 16:12:16 +0530 Message-ID: <1405334543-25509-2-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1405334543-25509-1-git-send-email-kishon@ti.com> References: <1405334543-25509-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: kishon@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Keerthy Add divider table to optfclk_pciephy_div clock. The 8th bit of CM_CLKMODE_APLL_PCIE can be programmed to either 0x0 or 0x1 based on if the divider value is 0x2 or 0x1. Figure 26-21. PCIe PHY Clock Generator Overview in vE of DRA7xx ES1.0 shows the block diagram of Clock Generator Subsystem of PCIe PHY module. The divider value if '1' should be programmed in order to get the correct PCIE_PHY_DIV_GCLK frequency (2.5GHz). Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index b03cfe4..7148e7c 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1170,6 +1170,7 @@ clocks = <&apll_pcie_ck>; #clock-cells = <0>; reg = <0x021c>; + ti,dividers = <2>, <1>; ti,bit-shift = <8>; ti,max-div = <2>; };