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[2.99.228.46]) by mx.google.com with ESMTPSA id gc5sm28672755wic.6.2014.07.14.01.48.55 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Jul 2014 01:48:56 -0700 (PDT) From: Srinivas Kandagatla To: Kishon Vijay Abraham I Cc: Grant Likely , Rob Herring , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-ide@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v3 2/2] phy: qcom: Update APQ8064 PHY device tree bindings Date: Mon, 14 Jul 2014 09:48:53 +0100 Message-Id: <1405327733-27537-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1405327664-27439-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1405327664-27439-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: srinivas.kandagatla@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on the APQ8064 family of SoCs Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/phy/qcom-phy.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/qcom-phy.txt b/Documentation/devicetree/bindings/phy/qcom-phy.txt index 76bfbd0..6bff1e0 100644 --- a/Documentation/devicetree/bindings/phy/qcom-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-phy.txt @@ -1,4 +1,4 @@ -Qualcomm IPQ806x SATA PHY Controller +Qualcomm IPQ806x/APQ8064 SATA PHY Controller ------------------------------------ SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. @@ -6,6 +6,7 @@ Each SATA PHY controller should have its own node. Required properties: - compatible: compatible list, contains "qcom,ipq806x-sata-phy" + or "qcom,apq8064-sata-phy". - reg: offset and length of the SATA PHY register set; - #phy-cells: must be zero - clocks: must be exactly one entry