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[209.132.180.67]) by mx.google.com with ESMTP id ff2si13387315pbc.132.2014.06.05.08.23.30; Thu, 05 Jun 2014 08:23:30 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752883AbaFEPX0 (ORCPT + 27 others); Thu, 5 Jun 2014 11:23:26 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:52524 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752320AbaFEPXW (ORCPT ); Thu, 5 Jun 2014 11:23:22 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s55FME4V001680; Thu, 5 Jun 2014 10:22:14 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s55FMDX2003846; Thu, 5 Jun 2014 10:22:13 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Thu, 5 Jun 2014 10:22:13 -0500 Received: from ula0393909.am.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s55FMCaR025466; Thu, 5 Jun 2014 10:22:12 -0500 From: Santosh Shilimkar To: CC: , , , , Santosh Shilimkar , Arnd Bergmann , Grant Likely , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Shawn Guo , Kumar Gala Subject: [PATCH] dt/documentation: add specification of dma bus information Date: Thu, 5 Jun 2014 11:22:00 -0400 Message-ID: <1401981720-6946-1-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: santosh.shilimkar@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Recently we introduced the generic device tree infrastructure for couple of DMA bus parameter, dma-ranges and dma-coherent. Update the documentation so that its useful for future users. The "dma-ranges" property is intended to be used for describing the configuration of DMA bus RAM addresses and its offset w.r.t CPU addresses. The "dma-coherent" property is intended to be used for identifying devices supported coherent DMA operations. Cc: Arnd Bergmann Cc: Grant Likely Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Shawn Guo Cc: Kumar Gala Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar Acked-by: Shawn Guo --- Documentation/devicetree/booting-without-of.txt | 60 +++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/Documentation/devicetree/booting-without-of.txt b/Documentation/devicetree/booting-without-of.txt index 1f013bd..f0120c1 100644 --- a/Documentation/devicetree/booting-without-of.txt +++ b/Documentation/devicetree/booting-without-of.txt @@ -51,6 +51,8 @@ Table of Contents VIII - Specifying device power management information (sleep property) + VIV - Specifying dma bus information + Appendix A - Sample SOC node for MPC8540 @@ -1332,6 +1334,64 @@ reasonably grouped in this manner, then create a virtual sleep controller (similar to an interrupt nexus, except that defining a standardized sleep-map should wait until its necessity is demonstrated). +VIV - Specifying dma bus information + +Some devices may have DMA memory range shifted relatively to the beginning of +RAM, or even placed outside of kernel RAM. For example, the Keystone 2 SoC +worked in LPAE mode with 4G memory has: +- RAM range: [0x8 0000 0000, 0x8 FFFF FFFF] +- DMA range: [ 0x8000 0000, 0xFFFF FFFF] +and DMA range is aliased into first 2G of RAM in HW. + +In such cases, DMA addresses translation should be performed between CPU phys +and DMA addresses. The "dma-ranges" property is intended to be used +for describing the configuration of such system in DT. + +In addition, each DMA master device on the DMA bus may or may not support +coherent DMA operations. The "dma-coherent" property is intended to be used +for identifying devices supported coherent DMA operations in DT. + +* DMA Bus master +Optional property: +- dma-ranges: encoded as arbitrary number of triplets of + (child-bus-address, parent-bus-address, length). Each triplet specified + describes a contiguous DMA address range. + The dma-ranges property is used to describe the direct memory access (DMA) + structure of a memory-mapped bus whose device tree parent can be accessed + from DMA operations originating from the bus. It provides a means of + defining a mapping or translation between the physical address space of + the bus and the physical address space of the parent of the bus. + (for more information see ePAPR specification) + +* DMA Bus child +Optional property: +- dma-ranges: value. if present - It means that DMA addresses + translation has to be enabled for this device. +- dma-coherent: Present if dma operations are coherent + +Example: +soc { + compatible = "ti,keystone","simple-bus"; + ranges = <0x0 0x0 0x0 0xc0000000>; + dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; + + [...] + + usb: usb@2680000 { + compatible = "ti,keystone-dwc3"; + + [...] + + dma-coherent; + dma-ranges; + + dwc3@2690000 { + compatible = "synopsys,dwc3"; + [...] + }; + }; +}; + Appendix A - Sample SOC node for MPC8540 ========================================