From patchwork Fri May 23 10:30:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 30689 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yh0-f71.google.com (mail-yh0-f71.google.com [209.85.213.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 781072066E for ; Fri, 23 May 2014 10:32:39 +0000 (UTC) Received: by mail-yh0-f71.google.com with SMTP id 29sf18115688yhl.2 for ; Fri, 23 May 2014 03:32:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=KzGrBoYjNpQXCProJ3BteBVGg+9bfCfzpxtAxKWswt8=; b=lD0Pq3rmpodTbTNqVr4Z3zs54PeSyYTQ798y42qz7QRkL8bK3sGUjmDGHsIZLGv8zU tWABzxahcAAdHHXjYnLbru61tT3jUOMjPcYWDLb9RxhSbEvaorj6rHFRIrXesHKIVhBC LD0Gps3DFspoz5hWRqNw9U4BuvLT4/VufXOC8a91bdtwryVbCKEpfEDDf+4xFIipCwAi m7NDr8wTNtS3ziR1BMOGSxtP7+u8+2G4Eds+pul6jtk2+fUTSg+vtjfM+CDu7v56zahd GJNUN1U92ChwO6u6J4svlPZEgt6wJZ9nTgllntnFeqBAbmR37jw8Gocm7ESWncOHVMIR sspw== X-Gm-Message-State: ALoCoQnAdxIijSTDkFm2/o+PAKVIKMm8UjitRVmEg3HUIib+0OUmmOa6Q9QRVEbbXz/oCmcpV5Ct X-Received: by 10.58.100.235 with SMTP id fb11mr1264948veb.33.1400841159243; Fri, 23 May 2014 03:32:39 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.32.67 with SMTP id g61ls1694630qgg.12.gmail; Fri, 23 May 2014 03:32:39 -0700 (PDT) X-Received: by 10.220.98.143 with SMTP id q15mr430534vcn.38.1400841159162; Fri, 23 May 2014 03:32:39 -0700 (PDT) Received: from mail-ve0-f172.google.com (mail-ve0-f172.google.com [209.85.128.172]) by mx.google.com with ESMTPS id io2si1373830vcb.84.2014.05.23.03.32.39 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 23 May 2014 03:32:39 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.172 as permitted sender) client-ip=209.85.128.172; Received: by mail-ve0-f172.google.com with SMTP id oz11so6004049veb.17 for ; Fri, 23 May 2014 03:32:39 -0700 (PDT) X-Received: by 10.58.29.234 with SMTP id n10mr3457398veh.16.1400841159085; Fri, 23 May 2014 03:32:39 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp19788vcb; Fri, 23 May 2014 03:32:38 -0700 (PDT) X-Received: by 10.69.26.103 with SMTP id ix7mr4509419pbd.41.1400841158092; Fri, 23 May 2014 03:32:38 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bg4si3275525pbb.67.2014.05.23.03.32.37 for ; Fri, 23 May 2014 03:32:37 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752344AbaEWKb4 (ORCPT + 27 others); Fri, 23 May 2014 06:31:56 -0400 Received: from mail-wg0-f49.google.com ([74.125.82.49]:48712 "EHLO mail-wg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752511AbaEWKbw (ORCPT ); Fri, 23 May 2014 06:31:52 -0400 Received: by mail-wg0-f49.google.com with SMTP id m15so4675124wgh.32 for ; Fri, 23 May 2014 03:31:51 -0700 (PDT) X-Received: by 10.180.94.226 with SMTP id df2mr2423116wib.1.1400841110983; Fri, 23 May 2014 03:31:50 -0700 (PDT) Received: from localhost.localdomain (AToulouse-654-1-404-187.w82-125.abo.wanadoo.fr. [82.125.3.187]) by mx.google.com with ESMTPSA id s9sm2200908wix.13.2014.05.23.03.31.49 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 23 May 2014 03:31:50 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, mingo@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 12/71] clocksource: sh_cmt: Replace hardcoded register values with macros Date: Fri, 23 May 2014 12:30:52 +0200 Message-Id: <1400841111-6683-12-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1400841111-6683-1-git-send-email-daniel.lezcano@linaro.org> References: <537F214C.8000700@linaro.org> <1400841111-6683-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.lezcano@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Laurent Pinchart Define symbolic macros for all used registers bits. Signed-off-by: Laurent Pinchart --- drivers/clocksource/sh_cmt.c | 56 +++++++++++++++++++++++++++++++++--------- 1 file changed, 44 insertions(+), 12 deletions(-) diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 879b8c2..ce00baa 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -114,6 +114,34 @@ struct sh_cmt_device { unsigned int num_channels; }; +#define SH_CMT16_CMCSR_CMF (1 << 7) +#define SH_CMT16_CMCSR_CMIE (1 << 6) +#define SH_CMT16_CMCSR_CKS8 (0 << 0) +#define SH_CMT16_CMCSR_CKS32 (1 << 0) +#define SH_CMT16_CMCSR_CKS128 (2 << 0) +#define SH_CMT16_CMCSR_CKS512 (3 << 0) +#define SH_CMT16_CMCSR_CKS_MASK (3 << 0) + +#define SH_CMT32_CMCSR_CMF (1 << 15) +#define SH_CMT32_CMCSR_OVF (1 << 14) +#define SH_CMT32_CMCSR_WRFLG (1 << 13) +#define SH_CMT32_CMCSR_STTF (1 << 12) +#define SH_CMT32_CMCSR_STPF (1 << 11) +#define SH_CMT32_CMCSR_SSIE (1 << 10) +#define SH_CMT32_CMCSR_CMS (1 << 9) +#define SH_CMT32_CMCSR_CMM (1 << 8) +#define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) +#define SH_CMT32_CMCSR_CMR_NONE (0 << 4) +#define SH_CMT32_CMCSR_CMR_DMA (1 << 4) +#define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) +#define SH_CMT32_CMCSR_CMR_MASK (3 << 4) +#define SH_CMT32_CMCSR_DBGIVD (1 << 3) +#define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) +#define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) +#define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) +#define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) +#define SH_CMT32_CMCSR_CKS_MASK (7 << 0) + static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) { return ioread16(base + (offs << 1)); @@ -140,8 +168,8 @@ static const struct sh_cmt_info sh_cmt_info[] = { [SH_CMT_16BIT] = { .model = SH_CMT_16BIT, .width = 16, - .overflow_bit = 0x80, - .clear_bits = ~0x80, + .overflow_bit = SH_CMT16_CMCSR_CMF, + .clear_bits = ~SH_CMT16_CMCSR_CMF, .read_control = sh_cmt_read16, .write_control = sh_cmt_write16, .read_count = sh_cmt_read16, @@ -150,8 +178,8 @@ static const struct sh_cmt_info sh_cmt_info[] = { [SH_CMT_32BIT] = { .model = SH_CMT_32BIT, .width = 32, - .overflow_bit = 0x8000, - .clear_bits = ~0xc000, + .overflow_bit = SH_CMT32_CMCSR_CMF, + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), .read_control = sh_cmt_read16, .write_control = sh_cmt_write16, .read_count = sh_cmt_read32, @@ -160,8 +188,8 @@ static const struct sh_cmt_info sh_cmt_info[] = { [SH_CMT_32BIT_FAST] = { .model = SH_CMT_32BIT_FAST, .width = 32, - .overflow_bit = 0x8000, - .clear_bits = ~0xc000, + .overflow_bit = SH_CMT32_CMCSR_CMF, + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), .read_control = sh_cmt_read16, .write_control = sh_cmt_write16, .read_count = sh_cmt_read32, @@ -170,8 +198,8 @@ static const struct sh_cmt_info sh_cmt_info[] = { [SH_CMT_48BIT] = { .model = SH_CMT_48BIT, .width = 32, - .overflow_bit = 0x8000, - .clear_bits = ~0xc000, + .overflow_bit = SH_CMT32_CMCSR_CMF, + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), .read_control = sh_cmt_read32, .write_control = sh_cmt_write32, .read_count = sh_cmt_read32, @@ -180,8 +208,8 @@ static const struct sh_cmt_info sh_cmt_info[] = { [SH_CMT_48BIT_GEN2] = { .model = SH_CMT_48BIT_GEN2, .width = 32, - .overflow_bit = 0x8000, - .clear_bits = ~0xc000, + .overflow_bit = SH_CMT32_CMCSR_CMF, + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), .read_control = sh_cmt_read32, .write_control = sh_cmt_write32, .read_count = sh_cmt_read32, @@ -295,10 +323,14 @@ static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate) /* configure channel, periodic mode and maximum timeout */ if (ch->cmt->info->width == 16) { *rate = clk_get_rate(ch->cmt->clk) / 512; - sh_cmt_write_cmcsr(ch, 0x43); + sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | + SH_CMT16_CMCSR_CKS512); } else { *rate = clk_get_rate(ch->cmt->clk) / 8; - sh_cmt_write_cmcsr(ch, 0x01a4); + sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | + SH_CMT32_CMCSR_CMTOUT_IE | + SH_CMT32_CMCSR_CMR_IRQ | + SH_CMT32_CMCSR_CKS_RCLK8); } sh_cmt_write_cmcor(ch, 0xffffffff);