From patchwork Thu May 22 16:47:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 30654 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ob0-f197.google.com (mail-ob0-f197.google.com [209.85.214.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 4813320671 for ; Thu, 22 May 2014 16:56:47 +0000 (UTC) Received: by mail-ob0-f197.google.com with SMTP id vb8sf16364678obc.8 for ; Thu, 22 May 2014 09:56:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=XNqrOCcd4knHaGbecKoIioLpnIyR7R223i6wHnKoSm0=; b=Z8LrydxX7MhELMH8U9P1G+Gyu9iwDadDqDZqMjJB257fYuFQvKPuE9zBH+fPFRhdnX lcOwK1S9x9E94/80INKJjAaK5w/kcsOGG6Ln5KUlhdTSTdDhP/eKtEfcJc2T7szArHjT WNBJDTPaFSe4dwtS6FT8DDEffLuzQEOhrwNt983eKO8RUDQ8l291ZCTaALbi/e7rT+N+ gZqqrP3qQ1mPQk7voyz9ebwJNh3H/QiKRuX8+PxsknTH3BM3rQ/sj1X2AtxAqbdQcRRC FJCSopotThrTDT2tzg1F6CK/HlmWtDO05ETcOmVwcdLW/36RjK4vVHKIqlo/7/EF0vq/ 4kFw== X-Gm-Message-State: ALoCoQnYoao+/7s9Frs06iGMTetz7JrYFNJlvotfrRaMXdQ7AK+bTg6Rr/iJLe4KFVJ9L3L6iC29 X-Received: by 10.182.227.131 with SMTP id sa3mr26226267obc.38.1400777806873; Thu, 22 May 2014 09:56:46 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.21.85 with SMTP id 79ls1359205qgk.41.gmail; Thu, 22 May 2014 09:56:46 -0700 (PDT) X-Received: by 10.52.238.161 with SMTP id vl1mr1306172vdc.88.1400777806725; Thu, 22 May 2014 09:56:46 -0700 (PDT) Received: from mail-vc0-f169.google.com (mail-vc0-f169.google.com [209.85.220.169]) by mx.google.com with ESMTPS id tg3si221686vcb.24.2014.05.22.09.56.46 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 22 May 2014 09:56:46 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.169 as permitted sender) client-ip=209.85.220.169; Received: by mail-vc0-f169.google.com with SMTP id ij19so4851710vcb.28 for ; Thu, 22 May 2014 09:56:46 -0700 (PDT) X-Received: by 10.220.250.203 with SMTP id mp11mr17028853vcb.2.1400777806639; Thu, 22 May 2014 09:56:46 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp215657vcb; Thu, 22 May 2014 09:56:46 -0700 (PDT) X-Received: by 10.68.197.134 with SMTP id iu6mr37482708pbc.164.1400777805908; Thu, 22 May 2014 09:56:45 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bv3si473883pad.79.2014.05.22.09.56.45 for ; Thu, 22 May 2014 09:56:45 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753415AbaEVQ4W (ORCPT + 27 others); Thu, 22 May 2014 12:56:22 -0400 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:48867 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752811AbaEVQsQ (ORCPT ); Thu, 22 May 2014 12:48:16 -0400 Received: from edgewater-inn.cambridge.arm.com (edgewater-inn.cambridge.arm.com [10.1.203.25]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id s4MGlWwo028171; Thu, 22 May 2014 17:47:32 +0100 (BST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 2FB9D1AE1278; Thu, 22 May 2014 17:47:34 +0100 (BST) From: Will Deacon To: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, monstr@monstr.eu, dhowells@redhat.com, broonie@linaro.org, benh@kernel.crashing.org, peterz@infradead.org, paulmck@linux.vnet.ibm.com, Will Deacon Subject: [PATCH v2 01/18] asm-generic: io: implement relaxed accessor macros as conditional wrappers Date: Thu, 22 May 2014 17:47:13 +0100 Message-Id: <1400777250-17335-2-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 1.9.2 In-Reply-To: <1400777250-17335-1-git-send-email-will.deacon@arm.com> References: <1400777250-17335-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: will.deacon@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , {read,write}{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds wrappers to asm-generic so that drivers can rely on the relaxed accessors being available, even if they don't always provide weaker ordering guarantees. Since some architectures both include asm-generic/io.h and define some relaxed accessors, the definitions here are conditional for the time being. Cc: Arnd Bergmann Signed-off-by: Will Deacon --- include/asm-generic/io.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index 975e1cc75edb..9ccedeb06522 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -53,18 +53,27 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) #endif #define readb __raw_readb +#ifndef readb_relaxed +#define readb_relaxed readb +#endif #define readw readw static inline u16 readw(const volatile void __iomem *addr) { return __le16_to_cpu(__raw_readw(addr)); } +#ifndef readw_relaxed +#define readw_relaxed readw +#endif #define readl readl static inline u32 readl(const volatile void __iomem *addr) { return __le32_to_cpu(__raw_readl(addr)); } +#ifndef readl_relaxed +#define readl_relaxed readl +#endif #ifndef __raw_writeb static inline void __raw_writeb(u8 b, volatile void __iomem *addr) @@ -88,8 +97,19 @@ static inline void __raw_writel(u32 b, volatile void __iomem *addr) #endif #define writeb __raw_writeb +#ifndef writeb_relaxed +#define writeb_relaxed writeb +#endif + #define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr) +#ifndef writew_relaxed +#define writew_relaxed writew +#endif + #define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr) +#ifndef writel_relaxed +#define writel_relaxed writel +#endif #ifdef CONFIG_64BIT #ifndef __raw_readq @@ -104,6 +124,9 @@ static inline u64 readq(const volatile void __iomem *addr) { return __le64_to_cpu(__raw_readq(addr)); } +#ifndef readq_relaxed +#define readq_relaxed readq +#endif #ifndef __raw_writeq static inline void __raw_writeq(u64 b, volatile void __iomem *addr) @@ -113,6 +136,9 @@ static inline void __raw_writeq(u64 b, volatile void __iomem *addr) #endif #define writeq(b, addr) __raw_writeq(__cpu_to_le64(b), addr) +#ifndef writeq_relaxed +#define writeq_relaxed writeq +#endif #endif /* CONFIG_64BIT */ #ifndef PCI_IOBASE