From patchwork Thu May 1 09:56:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 29448 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f70.google.com (mail-oa0-f70.google.com [209.85.219.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 0C17F203F3 for ; Thu, 1 May 2014 09:57:18 +0000 (UTC) Received: by mail-oa0-f70.google.com with SMTP id i4sf12438184oah.9 for ; Thu, 01 May 2014 02:57:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=CCch3szSebgnbKYlZ4xFIFARBVNbE8kpPKprOqRete4=; b=CQD5nmrMJoN3hZZKbB3wQekX8+SXn4jlwOm4XJ0hhMQfHBHFN/O4KMrg9xjK2StynB 0kyC1voT2UVV+7j7hAnN8lB3FszlPe9iDL4R4VzZ0kSKsn110vsRJ0mk03US5R7Q/Kkm L8my9wdyZfXSkZ4VR4RvvpR0f0V+pGnt2S0eissUTbb7l7Diu/roozDeYiA2wSMEwHoT c5SmE4NGu6jFdV0kB6xMkiq9CEwCJ3wJFzXbYSmEhWJojE4dU3vmD1RRqtwmVYkjEdhg wYnCZien2MBZKOiPz3R+arwJVY5DbA6OU7jTIbP0uVF04cSXBNt9yuz/j+PZzy9NRd/6 ES5Q== X-Gm-Message-State: ALoCoQls6iu/a1LlXEGKAjC8LC7Dn5Og4YlYgK5vUc0kp0cqIp/0OfGlpH+FVZ3uKWy9WOXqQzlW X-Received: by 10.182.128.166 with SMTP id np6mr5307560obb.16.1398938238589; Thu, 01 May 2014 02:57:18 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.102.87 with SMTP id v81ls1181099qge.0.gmail; Thu, 01 May 2014 02:57:18 -0700 (PDT) X-Received: by 10.53.1.69 with SMTP id be5mr6752776vdd.27.1398938238441; Thu, 01 May 2014 02:57:18 -0700 (PDT) Received: from mail-ve0-f172.google.com (mail-ve0-f172.google.com [209.85.128.172]) by mx.google.com with ESMTPS id bp12si5967348veb.135.2014.05.01.02.57.18 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 02:57:18 -0700 (PDT) Received-SPF: none (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) client-ip=209.85.128.172; Received: by mail-ve0-f172.google.com with SMTP id jy13so3601921veb.17 for ; Thu, 01 May 2014 02:57:18 -0700 (PDT) X-Received: by 10.58.1.97 with SMTP id 1mr8402079vel.23.1398938238338; Thu, 01 May 2014 02:57:18 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp12886vcb; Thu, 1 May 2014 02:57:17 -0700 (PDT) X-Received: by 10.180.91.161 with SMTP id cf1mr1437256wib.49.1398938237381; Thu, 01 May 2014 02:57:17 -0700 (PDT) Received: from mail-we0-f180.google.com (mail-we0-f180.google.com [74.125.82.180]) by mx.google.com with ESMTPS id lb4si10543715wjc.73.2014.05.01.02.57.17 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 02:57:17 -0700 (PDT) Received-SPF: none (google.com: lee.jones@linaro.org does not designate permitted sender hosts) client-ip=74.125.82.180; Received: by mail-we0-f180.google.com with SMTP id t61so2822151wes.25 for ; Thu, 01 May 2014 02:57:17 -0700 (PDT) X-Received: by 10.194.1.242 with SMTP id 18mr8392502wjp.22.1398938236968; Thu, 01 May 2014 02:57:16 -0700 (PDT) Received: from lee--X1.home (host109-148-238-223.range109-148.btcentralplus.com. [109.148.238.223]) by mx.google.com with ESMTPSA id bj5sm2696494wib.3.2014.05.01.02.57.14 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 02:57:15 -0700 (PDT) From: Lee Jones To: linux-kernel@vger.kernel.org Cc: computersforpeace@gmail.com, linux-mtd@lists.infradead.org, kernel@stlinux.com, Lee Jones Subject: [PATCH 05/47] mtd: nand: add ONFI NAND Timing Mode Specifications Date: Thu, 1 May 2014 10:56:12 +0100 Message-Id: <1398938214-17847-6-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1398938214-17847-1-git-send-email-lee.jones@linaro.org> References: <1398938214-17847-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch adds a new structure, 'nand_timing_spec', to capture the A/C timing characteristics of NAND devices. Unfortunately, there is no universally accepted standard for defining NAND timing parameters. Different datasheets list different sets of parameters. The ONFI standard gets close, but support is missing from some of the major NAND manufacturers (e.g. Samsung, Toshiba). Here we have followed broadly the ONFI timing definitions. We also provide specifications for the six standard ONFI timing modes, in terms of the new nand_timing_spec structure. This will allow fully automated configuration of the timing registers when using ONFI-compliant NAND. Signed-off-by: Lee Jones --- drivers/mtd/nand/stm_nand_bch.c | 167 +++++++++++++++++++++++++++++++++++++++ drivers/mtd/nand/stm_nand_regs.h | 30 +++++++ 2 files changed, 197 insertions(+) diff --git a/drivers/mtd/nand/stm_nand_bch.c b/drivers/mtd/nand/stm_nand_bch.c index 09a7fdb..2d6a81f 100644 --- a/drivers/mtd/nand/stm_nand_bch.c +++ b/drivers/mtd/nand/stm_nand_bch.c @@ -54,6 +54,173 @@ struct nandi_controller { /* 'page_buf' */ }; +/* ONFI define 6 timing modes */ +#define ST_NAND_ONFI_TIMING_MODES 6 + +/* + * ONFI NAND Timing Mode Specifications + * + * Note, 'tR' field (maximum page read time) is extracted from the ONFI + * parameter page during device probe. + */ +const struct nand_timing_spec st_nand_onfi_timing_specs[] = { + /* + * ONFI Timing Mode '0' (supported on all ONFI compliant devices) + */ + [0] = { + .tCLS = 50, + .tCS = 70, + .tALS = 50, + .tDS = 40, + .tWP = 50, + .tCLH = 20, + .tCH = 20, + .tALH = 20, + .tDH = 20, + .tWB = 200, + .tWH = 30, + .tWC = 100, + .tRP = 50, + .tREH = 30, + .tRC = 100, + .tREA = 40, + .tRHOH = 0, + .tCEA = 100, + .tCOH = 0, + .tCHZ = 100, + }, + + /* + * ONFI Timing Mode '1' + */ + [1] = { + .tCLS = 25, + .tCS = 35, + .tALS = 25, + .tDS = 20, + .tWP = 25, + .tCLH = 10, + .tCH = 10, + .tALH = 10, + .tDH = 10, + .tWB = 100, + .tWH = 15, + .tWC = 45, + .tRP = 25, + .tREH = 15, + .tRC = 50, + .tREA = 30, + .tRHOH = 15, + .tCEA = 45, + .tCOH = 15, + .tCHZ = 50, + }, + + /* + * ONFI Timing Mode '2' + */ + [2] = { + .tCLS = 15, + .tCS = 25, + .tALS = 15, + .tDS = 15, + .tWP = 17, + .tCLH = 10, + .tCH = 10, + .tALH = 10, + .tDH = 5, + .tWB = 100, + .tWH = 15, + .tWC = 35, + .tRP = 17, + .tREH = 16, + .tRC = 35, + .tREA = 25, + .tRHOH = 15, + .tCEA = 30, + .tCOH = 15, + .tCHZ = 50, + }, + + /* + * ONFI Timing Mode '3' + */ + [3] = { + .tCLS = 10, + .tCS = 25, + .tALS = 10, + .tDS = 10, + .tWP = 15, + .tCLH = 5, + .tCH = 5, + .tALH = 5, + .tDH = 5, + .tWB = 100, + .tWH = 10, + .tWC = 30, + .tRP = 15, + .tREH = 10, + .tRC = 30, + .tREA = 20, + .tRHOH = 15, + .tCEA = 25, + .tCOH = 15, + .tCHZ = 50, + }, + + /* + * ONFI Timing Mode '4' (EDO only) + */ + [4] = { + .tCLS = 10, + .tCS = 20, + .tALS = 10, + .tDS = 10, + .tWP = 12, + .tCLH = 5, + .tCH = 5, + .tALH = 5, + .tDH = 5, + .tWB = 100, + .tWH = 10, + .tWC = 25, + .tRP = 12, + .tREH = 10, + .tRC = 25, + .tREA = 20, + .tRHOH = 15, + .tCEA = 25, + .tCOH = 15, + .tCHZ = 30, + }, + + /* + * ONFI Timing Mode '5' (EDO only) + */ + [5] = { + .tCLS = 10, + .tCS = 15, + .tALS = 10, + .tDS = 7, + .tWP = 10, + .tCLH = 5, + .tCH = 5, + .tALH = 5, + .tDH = 5, + .tWB = 100, + .tWH = 7, + .tWC = 20, + .tRP = 10, + .tREH = 7, + .tRC = 20, + .tREA = 16, + .tRHOH = 15, + .tCEA = 25, + .tCOH = 15, + .tCHZ = 30, + } +}; + static int remap_named_resource(struct platform_device *pdev, char *name, void __iomem **io_ptr) diff --git a/drivers/mtd/nand/stm_nand_regs.h b/drivers/mtd/nand/stm_nand_regs.h index 2b0e069..e4951dc 100644 --- a/drivers/mtd/nand/stm_nand_regs.h +++ b/drivers/mtd/nand/stm_nand_regs.h @@ -299,4 +299,34 @@ #define FLEX_ADDR_ADD8_VALID (0x1 << 30) #define FLEX_ADDR_CSN (0x1 << 31) +/* + * NAND Device Timing Specification + * + * All values in nano seconds, except where specified. + */ +struct nand_timing_spec { + int tR; /* Max Page Read delay [us]*/ + int tCLS; /* Min CLE setup time */ + int tCS; /* Min CE setup time */ + int tALS; /* Min ALE setup time */ + int tDS; /* Min Data setup time */ + int tWP; /* Min WE pulse width */ + int tCLH; /* Min CLE hold time */ + int tCH; /* Min CE hold time */ + int tALH; /* Min ALE hold time */ + int tDH; /* Min Data hold time */ + int tWB; /* Max WE high to busy */ + int tWH; /* Min WE hold time */ + int tWC; /* Min Write cycle time */ + int tRP; /* Min RE pulse width */ + int tREH; /* Min RE high hold time */ + int tRC; /* Min Read cycle time */ + int tREA; /* Max Read access time */ + int tRHOH; /* Min RE high to output hold */ + int tCEA; /* Max CE access time */ + int tCOH; /* Min CE high to output hold */ + int tCHZ; /* Max CE high to output high Z */ + int tCSD; /* Min CE high to ALE/CLE don't care */ +}; + #endif /* STM_NANDC_REGS_H */