From patchwork Thu May 1 09:56:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 29453 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f72.google.com (mail-qa0-f72.google.com [209.85.216.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 6C91E203F3 for ; Thu, 1 May 2014 09:57:28 +0000 (UTC) Received: by mail-qa0-f72.google.com with SMTP id hw13sf822829qab.11 for ; Thu, 01 May 2014 02:57:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=jllkwrJcGWKWpsVFGLUOHipXBN/i3uKUc1305q6mP0M=; b=KTjEFERo0I3OcFf2WHWU2H4JO+gJH+d8wLy/m1/okZ0P12ql6NilqfYp69Kq5/Bj6O G74orrevCxN7q7WdcYCQVNuevWw/DaasihBXY4AYAU5G/PuN8F2cp38kcPHhR5vftO1e 2Cb+REKUPd2qyax2k3MDimfmZO9YLDzXRckzSVQuODoh+WkxcXtPsCQyu1nsrJ0jnYd2 Zh7M+gVrSpeFjGfukOjc8HYeUOpNzUMfLTvC5Xe+IsJHNfPNdwM//X1Dk+KAFg1rkJpJ RsYTuX7hSj663A/ZqktE5dqLsHmGtEyGx7d64MTvzMJ6t1Lr+T/1Os/ZYLDFQlfQNbzX wAWg== X-Gm-Message-State: ALoCoQl1fPntCNEUHXQzhb256NoMkS6VZ4MrCeBfG2xu5L29/09AKIAW5eKAmdDZzIgHn5k6Me2d X-Received: by 10.58.188.4 with SMTP id fw4mr5652875vec.9.1398938248211; Thu, 01 May 2014 02:57:28 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.49.231 with SMTP id q94ls1008953qga.28.gmail; Thu, 01 May 2014 02:57:28 -0700 (PDT) X-Received: by 10.52.142.10 with SMTP id rs10mr6796028vdb.3.1398938248115; Thu, 01 May 2014 02:57:28 -0700 (PDT) Received: from mail-ve0-f180.google.com (mail-ve0-f180.google.com [209.85.128.180]) by mx.google.com with ESMTPS id dy7si5970947vec.18.2014.05.01.02.57.28 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 02:57:28 -0700 (PDT) Received-SPF: none (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) client-ip=209.85.128.180; Received: by mail-ve0-f180.google.com with SMTP id db12so175518veb.39 for ; Thu, 01 May 2014 02:57:28 -0700 (PDT) X-Received: by 10.52.255.99 with SMTP id ap3mr6741669vdd.19.1398938248041; Thu, 01 May 2014 02:57:28 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp12896vcb; Thu, 1 May 2014 02:57:27 -0700 (PDT) X-Received: by 10.180.80.232 with SMTP id u8mr1490673wix.13.1398938247210; Thu, 01 May 2014 02:57:27 -0700 (PDT) Received: from mail-we0-f175.google.com (mail-we0-f175.google.com [74.125.82.175]) by mx.google.com with ESMTPS id by6si10524394wjb.241.2014.05.01.02.57.26 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 02:57:27 -0700 (PDT) Received-SPF: none (google.com: lee.jones@linaro.org does not designate permitted sender hosts) client-ip=74.125.82.175; Received: by mail-we0-f175.google.com with SMTP id q58so2900622wes.34 for ; Thu, 01 May 2014 02:57:26 -0700 (PDT) X-Received: by 10.180.96.39 with SMTP id dp7mr1579808wib.12.1398938246706; Thu, 01 May 2014 02:57:26 -0700 (PDT) Received: from lee--X1.home (host109-148-238-223.range109-148.btcentralplus.com. [109.148.238.223]) by mx.google.com with ESMTPSA id bj5sm2696494wib.3.2014.05.01.02.57.24 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 02:57:25 -0700 (PDT) From: Lee Jones To: linux-kernel@vger.kernel.org Cc: computersforpeace@gmail.com, linux-mtd@lists.infradead.org, kernel@stlinux.com, Lee Jones Subject: [PATCH 10/47] mtd: nand: stm_nand_bch: introduce and initialise some important data structures Date: Thu, 1 May 2014 10:56:17 +0100 Message-Id: <1398938214-17847-11-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1398938214-17847-1-git-send-email-lee.jones@linaro.org> References: <1398938214-17847-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Provide some more in-depth structures which will be used heavily within the driver. We also add a convenience function, used to set the default values. Signed-off-by: Lee Jones --- drivers/mtd/nand/stm_nand_bch.c | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/mtd/nand/stm_nand_bch.c b/drivers/mtd/nand/stm_nand_bch.c index 8e28da0..19d090c 100644 --- a/drivers/mtd/nand/stm_nand_bch.c +++ b/drivers/mtd/nand/stm_nand_bch.c @@ -21,10 +21,30 @@ #include #include #include +#include #include #include "stm_nand_regs.h" +/* Bad Block Table (BBT) */ +struct nandi_bbt_info { + uint32_t bbt_size; /* Size of bad-block table */ + uint32_t bbt_vers[2]; /* Version (Primary/Mirror) */ + uint32_t bbt_block[2]; /* Block No. (Primary/Mirror) */ + uint8_t *bbt; /* Table data */ +}; + +/* Collection of MTD/NAND device information */ +struct nandi_info { + struct mtd_info mtd; /* MTD info */ + struct nand_chip chip; /* NAND chip info */ + + struct nand_ecclayout ecclayout; /* MTD ECC layout */ + struct nandi_bbt_info bbt_info; /* Bad Block Table */ + int nr_parts; /* Number of MTD partitions */ + struct mtd_partition *parts; /* MTD partitions */ +}; + /* NANDi Controller (Hamming/BCH) */ struct nandi_controller { void __iomem *base; /* Controller base*/ @@ -60,6 +80,8 @@ struct nandi_controller { int cached_page; /* page number of page in */ /* 'page_buf' */ + + struct nandi_info info; /* NAND device info */ }; /* ONFI define 6 timing modes */ @@ -274,6 +296,37 @@ static void nandi_disable_interrupts(struct nandi_controller *nandi, writel(val, nandi->base + NANDBCH_INT_EN); } +static void nandi_set_mtd_defaults(struct nandi_controller *nandi, + struct mtd_info *mtd, struct nand_chip *chip) +{ + struct nandi_info *info = &nandi->info; + int i; + + /* ecclayout */ + info->ecclayout.eccbytes = mtd->oobsize; + for (i = 0; i < 64; i++) + info->ecclayout.eccpos[i] = i; + info->ecclayout.oobfree[0].offset = 0; + info->ecclayout.oobfree[0].length = 0; + chip->ecc.mode = NAND_ECC_HW + + /* nand_chip */ + chip->controller = &chip->hwcontrol; + spin_lock_init(&chip->controller->lock); + init_waitqueue_head(&chip->controller->wq); + chip->state = FL_READY; + chip->priv = nandi; + chip->ecc.layout = &info->ecclayout; + chip->options |= NAND_NO_SUBPAGE_WRITE; + + /* mtd_info */ + mtd->owner = THIS_MODULE; + mtd->type = MTD_NANDFLASH; + mtd->flags = MTD_CAP_NANDFLASH; + mtd->ecclayout = &info->ecclayout; + mtd->subpage_sft = 0; +} + static void nandi_clk_enable(struct nandi_controller *nandi) { if (nandi->emi_clk) @@ -438,7 +491,11 @@ static int stm_nand_bch_probe(struct platform_device *pdev) { struct stm_plat_nand_bch_data *pdata = pdev->dev.platform_data; struct stm_nand_bank_data *bank; + struct nandi_bbt_info *bbt_info; struct nandi_controller *nandi; + struct nandi_info *info; + struct nand_chip *chip; + struct mtd_info *mtd; nandi = nandi_init_resources(pdev); if (IS_ERR(nandi)) { @@ -453,6 +510,16 @@ static int stm_nand_bch_probe(struct platform_device *pdev) if (bank) nandi_init_controller(nandi, bank->csn); + info = &nandi->info; + chip = &info->chip; + bbt_info = &info->bbt_info; + mtd = &info->mtd; + mtd->priv = chip; + mtd->name = dev_name(&pdev->dev); + mtd->dev.parent = &pdev->dev; + + nandi_set_mtd_defaults(nandi, mtd, chip); + return 0; }