From patchwork Wed Jan 22 14:11:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean Pihet X-Patchwork-Id: 23525 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f70.google.com (mail-oa0-f70.google.com [209.85.219.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 411E9218CB for ; Wed, 22 Jan 2014 14:11:38 +0000 (UTC) Received: by mail-oa0-f70.google.com with SMTP id m1sf1546044oag.5 for ; Wed, 22 Jan 2014 06:11:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=1KMz+Q5O6xe9nNNIbIWXVZbUdYDE8F6M2FVHqLkoLpU=; b=ivSdNX8UsTjkHmNpuRDtLAmQ2zUAbZa26JRMCnHsnZ6VsyQ1GtDBWtUYubYmeVV2wn u13OBa8x4UmJ0Ct+1yD9Q0qltPYhBO7hXkZoTCkQVwQQqkOTWlJ1LfFq3KRbTsQyW0UT ddIZhlHlc7VRxHfUHOG3Kq5l6MSY8B2qBmtlJgA9b1hHhGL/7nuxS8jdpy9P0FL/4RD0 bb36wRDAzek6FbJqMTZEDOxiVezU04pjpuTuS8ga4aAe/+RkBV9QO4oJCRMyzShhb+MO elM/3SNI6xjb0XY0lJIA12etQVbDLh2zsEJ+kzHeZvE5eZDUB40Vxx0OcqqWt41W7DFV SNjQ== X-Gm-Message-State: ALoCoQnC+txIEZvfJMT+74vnGz7oyqh18KTij+De8oX6SO+mM43NlsjQR2nMoBLoMthXAWu+Q1Pm X-Received: by 10.50.112.10 with SMTP id im10mr9788953igb.2.1390399897430; Wed, 22 Jan 2014 06:11:37 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.28.6 with SMTP id 6ls84338qgy.16.gmail; Wed, 22 Jan 2014 06:11:37 -0800 (PST) X-Received: by 10.58.106.70 with SMTP id gs6mr1076488veb.28.1390399897303; Wed, 22 Jan 2014 06:11:37 -0800 (PST) Received: from mail-vb0-f54.google.com (mail-vb0-f54.google.com [209.85.212.54]) by mx.google.com with ESMTPS id gq1si4614106vec.23.2014.01.22.06.11.37 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 22 Jan 2014 06:11:37 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.54 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.54; Received: by mail-vb0-f54.google.com with SMTP id w20so245010vbb.27 for ; Wed, 22 Jan 2014 06:11:37 -0800 (PST) X-Received: by 10.221.34.211 with SMTP id st19mr1053309vcb.5.1390399897218; Wed, 22 Jan 2014 06:11:37 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp187094vcz; Wed, 22 Jan 2014 06:11:36 -0800 (PST) X-Received: by 10.15.24.72 with SMTP id i48mr321867eeu.74.1390399895971; Wed, 22 Jan 2014 06:11:35 -0800 (PST) Received: from mail-ea0-f170.google.com (mail-ea0-f170.google.com [209.85.215.170]) by mx.google.com with ESMTPS id u4si17665879eeo.170.2014.01.22.06.11.35 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 22 Jan 2014 06:11:35 -0800 (PST) Received-SPF: neutral (google.com: 209.85.215.170 is neither permitted nor denied by best guess record for domain of jean.pihet@linaro.org) client-ip=209.85.215.170; Received: by mail-ea0-f170.google.com with SMTP id k10so4615908eaj.15 for ; Wed, 22 Jan 2014 06:11:35 -0800 (PST) X-Received: by 10.14.209.129 with SMTP id s1mr1718327eeo.21.1390399895544; Wed, 22 Jan 2014 06:11:35 -0800 (PST) Received: from localhost.localdomain (80.58-241-81.adsl-dyn.isp.belgacom.be. [81.241.58.80]) by mx.google.com with ESMTPSA id d43sm27572324eeo.12.2014.01.22.06.11.33 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 22 Jan 2014 06:11:34 -0800 (PST) From: Jean Pihet To: linux-kernel@vger.kernel.org, linaro-kernel@lists.linaro.org, linux-arm-kernel@lists.infradead.org, Arnaldo , Ingo Molnar , Jiri Olsa , Will Deacon Cc: patches@linaro.org, Jean Pihet , Jean Pihet Subject: [PATCH 1/4] ARM64: perf: add support for perf registers API Date: Wed, 22 Jan 2014 15:11:16 +0100 Message-Id: <1390399879-5109-2-git-send-email-jean.pihet@linaro.org> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1390399879-5109-1-git-send-email-jean.pihet@linaro.org> References: <1390399879-5109-1-git-send-email-jean.pihet@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: jean.pihet@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.54 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Jean Pihet This patch implements the functions required for the perf registers API, allowing the perf tool to interface kernel register dumps with libunwind in order to provide userspace backtracing. Compat mode is also supported. Only the general purpose user space registers are exported, i.e.: PERF_REG_ARM_X0, ... PERF_REG_ARM_X28, PERF_REG_ARM_FP, PERF_REG_ARM_LR, PERF_REG_ARM_SP, PERF_REG_ARM_PC and not the PERF_REG_ARM_V* registers. Signed-off-by: Jean Pihet Cc: Will Deacon --- arch/arm64/Kconfig | 2 ++ arch/arm64/include/asm/ptrace.h | 1 + arch/arm64/include/uapi/asm/Kbuild | 1 + arch/arm64/include/uapi/asm/perf_regs.h | 40 ++++++++++++++++++++++++++++++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/perf_regs.c | 44 +++++++++++++++++++++++++++++++++ 6 files changed, 89 insertions(+) create mode 100644 arch/arm64/include/uapi/asm/perf_regs.h create mode 100644 arch/arm64/kernel/perf_regs.c diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index dd4327f..e9899bb 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -37,6 +37,8 @@ config ARM64 select HAVE_HW_BREAKPOINT if PERF_EVENTS select HAVE_MEMBLOCK select HAVE_PERF_EVENTS + select HAVE_PERF_REGS + select HAVE_PERF_USER_STACK_DUMP select IRQ_DOMAIN select MODULES_USE_ELF_RELA select NO_BOOTMEM diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index 0e7fa49..fbb0020 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -68,6 +68,7 @@ /* Architecturally defined mapping between AArch32 and AArch64 registers */ #define compat_usr(x) regs[(x)] +#define compat_fp regs[11] #define compat_sp regs[13] #define compat_lr regs[14] #define compat_sp_hyp regs[15] diff --git a/arch/arm64/include/uapi/asm/Kbuild b/arch/arm64/include/uapi/asm/Kbuild index e4b78bd..942376d 100644 --- a/arch/arm64/include/uapi/asm/Kbuild +++ b/arch/arm64/include/uapi/asm/Kbuild @@ -9,6 +9,7 @@ header-y += byteorder.h header-y += fcntl.h header-y += hwcap.h header-y += kvm_para.h +header-y += perf_regs.h header-y += param.h header-y += ptrace.h header-y += setup.h diff --git a/arch/arm64/include/uapi/asm/perf_regs.h b/arch/arm64/include/uapi/asm/perf_regs.h new file mode 100644 index 0000000..172b831 --- /dev/null +++ b/arch/arm64/include/uapi/asm/perf_regs.h @@ -0,0 +1,40 @@ +#ifndef _ASM_ARM64_PERF_REGS_H +#define _ASM_ARM64_PERF_REGS_H + +enum perf_event_arm_regs { + PERF_REG_ARM64_X0, + PERF_REG_ARM64_X1, + PERF_REG_ARM64_X2, + PERF_REG_ARM64_X3, + PERF_REG_ARM64_X4, + PERF_REG_ARM64_X5, + PERF_REG_ARM64_X6, + PERF_REG_ARM64_X7, + PERF_REG_ARM64_X8, + PERF_REG_ARM64_X9, + PERF_REG_ARM64_X10, + PERF_REG_ARM64_X11, + PERF_REG_ARM64_X12, + PERF_REG_ARM64_X13, + PERF_REG_ARM64_X14, + PERF_REG_ARM64_X15, + PERF_REG_ARM64_X16, + PERF_REG_ARM64_X17, + PERF_REG_ARM64_X18, + PERF_REG_ARM64_X19, + PERF_REG_ARM64_X20, + PERF_REG_ARM64_X21, + PERF_REG_ARM64_X22, + PERF_REG_ARM64_X23, + PERF_REG_ARM64_X24, + PERF_REG_ARM64_X25, + PERF_REG_ARM64_X26, + PERF_REG_ARM64_X27, + PERF_REG_ARM64_X28, + PERF_REG_ARM64_X29, + PERF_REG_ARM64_LR, + PERF_REG_ARM64_SP, + PERF_REG_ARM64_PC, + PERF_REG_ARM64_MAX, +}; +#endif /* _ASM_ARM64_PERF_REGS_H */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 2d4554b..9a5d592 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -15,6 +15,7 @@ arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \ sys_compat.o arm64-obj-$(CONFIG_MODULES) += arm64ksyms.o module.o arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o +arm64-obj-$(CONFIG_PERF_EVENTS) += perf_regs.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/arm64/kernel/perf_regs.c b/arch/arm64/kernel/perf_regs.c new file mode 100644 index 0000000..f2d6f0a --- /dev/null +++ b/arch/arm64/kernel/perf_regs.c @@ -0,0 +1,44 @@ +#include +#include +#include +#include +#include +#include + +u64 perf_reg_value(struct pt_regs *regs, int idx) +{ + if (WARN_ON_ONCE((u32)idx >= PERF_REG_ARM64_MAX)) + return 0; + + /* + * Compat (i.e. 32 bit) mode: + * - PC has been set in the pt_regs struct in kernel_entry, + * - Handle SP and LR here. + */ + if (compat_user_mode(regs)) { + if ((u32)idx == PERF_REG_ARM64_SP) + return regs->compat_sp; + if ((u32)idx == PERF_REG_ARM64_LR) + return regs->compat_lr; + } + + return regs->regs[idx]; +} + +#define REG_RESERVED (~((1ULL << PERF_REG_ARM64_MAX) - 1)) + +int perf_reg_validate(u64 mask) +{ + if (!mask || mask & REG_RESERVED) + return -EINVAL; + + return 0; +} + +u64 perf_reg_abi(struct task_struct *task) +{ + if (is_compat_thread(task_thread_info(task))) + return PERF_SAMPLE_REGS_ABI_32; + else + return PERF_SAMPLE_REGS_ABI_64; +}