From patchwork Thu Nov 21 22:53:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 21667 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ob0-f199.google.com (mail-ob0-f199.google.com [209.85.214.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1B97D20E7C for ; Thu, 21 Nov 2013 22:53:45 +0000 (UTC) Received: by mail-ob0-f199.google.com with SMTP id gq1sf1455524obb.10 for ; Thu, 21 Nov 2013 14:53:45 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=j1vgLIa524B6Kz0wEFfSDa0s2H1caxnIn47vSkY96KI=; b=BxpY+dCoNH+CF9xlH29VC2JTVmXlJ67zCeotuEvCyL5wyWTBgvKNAhHvgA98OBhvzt 8rNNVUlkDDxFIM9rGstlMyg8m82FyFwYaVhzA+ojYQ8tCcoNqoXCfRvKygBfB7JkIkeX 3hgg4Qh4Va85sRZZTySxd5lyylqKP0lYLrOA24FYqgjTmKpjMGt7Lt31OMi0JNUYJnCD mT9s61OJELoL+oCfN+IcqsSPIRkPn4nOBZOdJ2g9qJUzuoqOUkGO63xuQqFxrJwzDfGu ndg6Ff2lbIbeRgh/QbMc5frBmMi9/p5G03N+KBK2jmyOCWLUVTaBa/zR0zoG0Qs34cU/ N19A== X-Gm-Message-State: ALoCoQkeagk1PJXfXjeXEFv6Hpr8raThJOj8n0Qb8cUXgX0tuXQTZ1JGhAZGZ/C5P4Z/KZWn0Gjg X-Received: by 10.182.109.200 with SMTP id hu8mr3186639obb.20.1385074424974; Thu, 21 Nov 2013 14:53:44 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.96.101 with SMTP id dr5ls688783qeb.80.gmail; Thu, 21 Nov 2013 14:53:44 -0800 (PST) X-Received: by 10.52.116.74 with SMTP id ju10mr6787841vdb.20.1385074424825; Thu, 21 Nov 2013 14:53:44 -0800 (PST) Received: from mail-vb0-f43.google.com (mail-vb0-f43.google.com [209.85.212.43]) by mx.google.com with ESMTPS id e3si11511915vek.93.2013.11.21.14.53.44 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 21 Nov 2013 14:53:44 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.43 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.43; Received: by mail-vb0-f43.google.com with SMTP id q12so329056vbe.16 for ; Thu, 21 Nov 2013 14:53:44 -0800 (PST) X-Received: by 10.52.157.232 with SMTP id wp8mr6782034vdb.4.1385074424716; Thu, 21 Nov 2013 14:53:44 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp32235vcz; Thu, 21 Nov 2013 14:53:44 -0800 (PST) X-Received: by 10.194.11.38 with SMTP id n6mr7723886wjb.25.1385074423406; Thu, 21 Nov 2013 14:53:43 -0800 (PST) Received: from mail-wi0-f180.google.com (mail-wi0-f180.google.com [209.85.212.180]) by mx.google.com with ESMTPS id lm19si1598968wic.26.2013.11.21.14.53.42 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 21 Nov 2013 14:53:43 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.180 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=209.85.212.180; Received: by mail-wi0-f180.google.com with SMTP id hm4so1832875wib.13 for ; Thu, 21 Nov 2013 14:53:42 -0800 (PST) X-Received: by 10.194.11.38 with SMTP id n6mr7723846wjb.25.1385074422703; Thu, 21 Nov 2013 14:53:42 -0800 (PST) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id nb16sm9741845wic.0.2013.11.21.14.53.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Nov 2013 14:53:42 -0800 (PST) From: Linus Walleij To: linux-kernel@vger.kernel.org, Thomas Gleixner Cc: Linus Walleij Subject: [PATCH RESEND] irqchip: versatile FPGA: support cascaded interrupts from DT Date: Thu, 21 Nov 2013 23:53:35 +0100 Message-Id: <1385074415-1264-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.43 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The Versatile FPGA interrupt controller supports cascading interrupts, i.e. that its output is connected to the input of another interrupt controller. This makes it possible to pass a parent interrupt from the device tree and print it in the boot log if applicable. Cc: Thomas Gleixner Signed-off-by: Linus Walleij --- TGLX: I can take this through ARM SoC if you're happy with it and prefer it that way, but it merges just as fine as it is on the IRQ tree. --- .../devicetree/bindings/arm/versatile-fpga-irq.txt | 5 +++++ drivers/irqchip/irq-versatile-fpga.c | 15 +++++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt index 9989eda755d9..c9cf605bb995 100644 --- a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt +++ b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt @@ -29,3 +29,8 @@ pic: pic@14000000 { clear-mask = <0xffffffff>; valid-mask = <0x003fffff>; }; + +Optional properties: +- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ + output is simply connected to the input of another IRQ controller, + then the parent IRQ shall be specified in this property. diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c index 47a52ab580d8..3ae2bb8d9cf2 100644 --- a/drivers/irqchip/irq-versatile-fpga.c +++ b/drivers/irqchip/irq-versatile-fpga.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -167,8 +168,12 @@ void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start, f->used_irqs++; } - pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n", + pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs", fpga_irq_id, name, base, f->used_irqs); + if (parent_irq != -1) + pr_cont(", parent IRQ: %d\n", parent_irq); + else + pr_cont("\n"); fpga_irq_id++; } @@ -180,6 +185,7 @@ int __init fpga_irq_of_init(struct device_node *node, void __iomem *base; u32 clear_mask; u32 valid_mask; + int parent_irq; if (WARN_ON(!node)) return -ENODEV; @@ -193,7 +199,12 @@ int __init fpga_irq_of_init(struct device_node *node, if (of_property_read_u32(node, "valid-mask", &valid_mask)) valid_mask = 0; - fpga_irq_init(base, node->name, 0, -1, valid_mask, node); + /* Some chips are cascaded from a parent IRQ */ + parent_irq = irq_of_parse_and_map(node, 0); + if (!parent_irq) + parent_irq = -1; + + fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node); writel(clear_mask, base + IRQ_ENABLE_CLEAR); writel(clear_mask, base + FIQ_ENABLE_CLEAR);