From patchwork Thu Nov 7 09:01:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 21395 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qe0-f69.google.com (mail-qe0-f69.google.com [209.85.128.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 2BEA5244F2 for ; Thu, 7 Nov 2013 09:01:32 +0000 (UTC) Received: by mail-qe0-f69.google.com with SMTP id 6sf416657qeb.8 for ; Thu, 07 Nov 2013 01:01:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=anKBkFzBppd0ohEcCXc37cGn9LjMVaOM5EIXt/wHVPg=; b=g7YV9RBbpnzvGzBuP2JFnI8mRIss6kZBdald6NtW02/jjgr4g6qFzD8Sa50hASLgT9 /sq2LKgWrPyR5uxHcMxiC0+CQFnPXxL1mMjt+ArKK22DPdUWytduRZBZeToWZ0ccMvU/ PjbFZAb/4OYqsY2alQ9AKzh5f0ZcEYII/FHBHDpvYCjMU41GR9GBJ+JlziyPvW7mdGU3 79dCSpmPLQz52sRIxMy+yFeq7d3SgKADz/4mmbU69UunMJqfdrLYJuz88DovhIYyHMJG TWoRxk40K0DnStsB43UkFffeJwquj2I7tX4yK9QZMAw6ldH2S2l8SmRB1PhZaMV3Rxiv 9VRg== X-Gm-Message-State: ALoCoQn8AkbQb+5imLmlOhSYUunaSPNV6UBZv6Iwe4AbtOx0lTAGU+iyMq6t0Qpsc1bb195cGtl1 X-Received: by 10.52.248.195 with SMTP id yo3mr2924312vdc.1.1383814892577; Thu, 07 Nov 2013 01:01:32 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.18.199 with SMTP id y7ls1031730qed.30.gmail; Thu, 07 Nov 2013 01:01:32 -0800 (PST) X-Received: by 10.58.67.168 with SMTP id o8mr5967102vet.22.1383814892344; Thu, 07 Nov 2013 01:01:32 -0800 (PST) Received: from mail-vc0-f173.google.com (mail-vc0-f173.google.com [209.85.220.173]) by mx.google.com with ESMTPS id lr1si1264989vcb.94.2013.11.07.01.01.32 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 07 Nov 2013 01:01:32 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.173; Received: by mail-vc0-f173.google.com with SMTP id lh4so149721vcb.4 for ; Thu, 07 Nov 2013 01:01:32 -0800 (PST) X-Received: by 10.221.18.70 with SMTP id qf6mr63823vcb.37.1383814891963; Thu, 07 Nov 2013 01:01:31 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp4825vcz; Thu, 7 Nov 2013 01:01:31 -0800 (PST) X-Received: by 10.180.221.106 with SMTP id qd10mr1615718wic.57.1383814890344; Thu, 07 Nov 2013 01:01:30 -0800 (PST) Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by mx.google.com with ESMTPS id w2si6599490wix.34.2013.11.07.01.01.29 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 07 Nov 2013 01:01:30 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.171 is neither permitted nor denied by best guess record for domain of daniel.lezcano@linaro.org) client-ip=209.85.212.171; Received: by mail-wi0-f171.google.com with SMTP id f4so284688wiw.16 for ; Thu, 07 Nov 2013 01:01:29 -0800 (PST) X-Received: by 10.194.110.138 with SMTP id ia10mr2630508wjb.3.1383814889507; Thu, 07 Nov 2013 01:01:29 -0800 (PST) Received: from mai.home (AToulouse-654-1-515-7.w109-220.abo.wanadoo.fr. [109.220.114.7]) by mx.google.com with ESMTPSA id q3sm33073173wib.5.2013.11.07.01.01.27 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 07 Nov 2013 01:01:28 -0800 (PST) From: Daniel Lezcano To: rostedt@goodmis.org Cc: fweisbec@gmail.com, mingo@redhat.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patches@linaro.org, linaro-kernel@lists.linaro.org, shaojie.sun@linaro.org, broonie@linaro.org Subject: [PATCH V3] ARM: trace: Add tracepoint for the Inter Processor Interrupt Date: Thu, 7 Nov 2013 10:01:27 +0100 Message-Id: <1383814887-15415-1-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.lezcano@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The Inter Processor Interrupt is used on ARM to tell another processor to do a specific action. This is mainly used to emulate a timer interrupt on an idle cpu, force a cpu to reschedule or run a function on another processor context. Add a tracepoint when raising an IPI and in the entry/exit handler functions. When a cpu raises an IPI, the targeted cpus is an interesting information, the cpumask conversion in hexa is added in the trace using the cpumask_scnprintf function. Tested-on Vexpress TC2 (5 processors). Tested-on u8500 (2 processors). Signed-off-by: Daniel Lezcano --- arch/arm/include/asm/smp.h | 9 ++++ arch/arm/kernel/smp.c | 34 +++++++------ arch/arm64/include/asm/smp.h | 7 +++ arch/arm64/kernel/smp.c | 21 ++++++-- include/trace/events/ipi.h | 112 ++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 164 insertions(+), 19 deletions(-) create mode 100644 include/trace/events/ipi.h diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index a8cae71c..788706c 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -18,6 +18,15 @@ # error " included in non-SMP build" #endif +enum ipi_msg_type { + IPI_WAKEUP, + IPI_TIMER, + IPI_RESCHEDULE, + IPI_CALL_FUNC, + IPI_CALL_FUNC_SINGLE, + IPI_CPU_STOP, +}; + #define raw_smp_processor_id() (current_thread_info()->cpu) struct seq_file; diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 72024ea..9ca8ce8 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -46,6 +46,9 @@ #include #include +#define CREATE_TRACE_POINTS +#include + /* * as from 2.5, kernels no longer have an init_tasks structure * so we need some other way of telling a new secondary core @@ -59,15 +62,6 @@ struct secondary_data secondary_data; */ volatile int pen_release = -1; -enum ipi_msg_type { - IPI_WAKEUP, - IPI_TIMER, - IPI_RESCHEDULE, - IPI_CALL_FUNC, - IPI_CALL_FUNC_SINGLE, - IPI_CPU_STOP, -}; - static DECLARE_COMPLETION(cpu_running); static struct smp_operations smp_ops; @@ -433,19 +427,25 @@ void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) smp_cross_call = fn; } +static void ipi_raise(const struct cpumask *mask, int ipinr) +{ + trace_ipi_raise(mask, ipinr); + smp_cross_call(mask, ipinr); +} + void arch_send_call_function_ipi_mask(const struct cpumask *mask) { - smp_cross_call(mask, IPI_CALL_FUNC); + ipi_raise(mask, IPI_CALL_FUNC); } void arch_send_wakeup_ipi_mask(const struct cpumask *mask) { - smp_cross_call(mask, IPI_WAKEUP); + ipi_raise(mask, IPI_WAKEUP); } void arch_send_call_function_single_ipi(int cpu) { - smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); + ipi_raise(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); } static const char *ipi_types[NR_IPI] = { @@ -487,7 +487,7 @@ u64 smp_irq_stat_cpu(unsigned int cpu) #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST void tick_broadcast(const struct cpumask *mask) { - smp_cross_call(mask, IPI_TIMER); + ipi_raise(mask, IPI_TIMER); } #endif @@ -528,6 +528,8 @@ void handle_IPI(int ipinr, struct pt_regs *regs) unsigned int cpu = smp_processor_id(); struct pt_regs *old_regs = set_irq_regs(regs); + trace_ipi_handler_entry(ipinr); + if (ipinr < NR_IPI) __inc_irq_stat(cpu, ipi_irqs[ipinr]); @@ -571,11 +573,13 @@ void handle_IPI(int ipinr, struct pt_regs *regs) break; } set_irq_regs(old_regs); + + trace_ipi_handler_exit(ipinr); } void smp_send_reschedule(int cpu) { - smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); + ipi_raise(cpumask_of(cpu), IPI_RESCHEDULE); } void smp_send_stop(void) @@ -586,7 +590,7 @@ void smp_send_stop(void) cpumask_copy(&mask, cpu_online_mask); cpumask_clear_cpu(smp_processor_id(), &mask); if (!cpumask_empty(&mask)) - smp_cross_call(&mask, IPI_CPU_STOP); + ipi_raise(&mask, IPI_CPU_STOP); /* Wait up to one second for other CPUs to stop */ timeout = USEC_PER_SEC; diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 4b8023c..7ebaa3a 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -24,6 +24,13 @@ # error " included in non-SMP build" #endif +enum ipi_msg_type { + IPI_RESCHEDULE, + IPI_CALL_FUNC, + IPI_CALL_FUNC_SINGLE, + IPI_CPU_STOP, +}; + #define raw_smp_processor_id() (current_thread_info()->cpu) struct seq_file; diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 78db90d..c987b9f 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -48,6 +48,9 @@ #include #include +#define CREATE_TRACE_POINTS +#include + /* * as from 2.5, kernels no longer have an init_tasks structure * so we need some other way of telling a new secondary core @@ -426,14 +429,20 @@ void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) smp_cross_call = fn; } +static void ipi_raise(const struct cpumask *mask, int ipinr) +{ + trace_ipi_raise(mask, ipinr); + smp_cross_call(mask, ipinr); +} + void arch_send_call_function_ipi_mask(const struct cpumask *mask) { - smp_cross_call(mask, IPI_CALL_FUNC); + ipi_raise(mask, IPI_CALL_FUNC); } void arch_send_call_function_single_ipi(int cpu) { - smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); + ipi_raise(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); } static const char *ipi_types[NR_IPI] = { @@ -501,6 +510,8 @@ void handle_IPI(int ipinr, struct pt_regs *regs) unsigned int cpu = smp_processor_id(); struct pt_regs *old_regs = set_irq_regs(regs); + trace_ipi_handler_entry(ipinr); + if (ipinr >= IPI_RESCHEDULE && ipinr < IPI_RESCHEDULE + NR_IPI) __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_RESCHEDULE]); @@ -532,11 +543,13 @@ void handle_IPI(int ipinr, struct pt_regs *regs) break; } set_irq_regs(old_regs); + + trace_ipi_handler_exit(ipinr); } void smp_send_reschedule(int cpu) { - smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); + ipi_raise(cpumask_of(cpu), IPI_RESCHEDULE); } void smp_send_stop(void) @@ -549,7 +562,7 @@ void smp_send_stop(void) cpumask_copy(&mask, cpu_online_mask); cpu_clear(smp_processor_id(), mask); - smp_cross_call(&mask, IPI_CPU_STOP); + ipi_raise(&mask, IPI_CPU_STOP); } /* Wait up to one second for other CPUs to stop */ diff --git a/include/trace/events/ipi.h b/include/trace/events/ipi.h new file mode 100644 index 0000000..fa22d4f --- /dev/null +++ b/include/trace/events/ipi.h @@ -0,0 +1,112 @@ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM ipi + +#if !defined(_TRACE_IPI_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_IPI_H + +#include + +#define ipi_name(ipinr) { IPI_##ipinr, #ipinr } +#define show_ipi_name(val) \ + __print_symbolic(val, \ + ipi_name(WAKEUP), \ + ipi_name(TIMER), \ + ipi_name(RESCHEDULE), \ + ipi_name(CALL_FUNC), \ + ipi_name(CALL_FUNC_SINGLE), \ + ipi_name(CPU_STOP)) + +#define show_cpumask(srcp) \ + ({ \ + char *buf = __get_dynamic_array(buf); \ + cpumask_scnprintf(buf, NR_CPUS, srcp); \ + buf; \ + }) + +DECLARE_EVENT_CLASS(ipi, + + TP_PROTO(int ipinr), + + TP_ARGS(ipinr), + + TP_STRUCT__entry( + __field(int, ipinr) + ), + + TP_fast_assign( + __entry->ipinr = ipinr; + ), + + TP_printk("ipi=%d, name=%s", __entry->ipinr, + show_ipi_name(__entry->ipinr)) +); + +/** + * ipi_handle_entry - called right before the IPI handler + * @ipinr: the IPI number + * + * The @ipinr value must be valid and the action name associated with + * the IPI value is given in the trace. + */ +DEFINE_EVENT_CONDITION(ipi, ipi_handler_entry, + + TP_PROTO(int ipinr), + + TP_ARGS(ipinr), + + TP_CONDITION(ipinr < NR_IPI && ipinr >= 0) +); + +/** + * ipi_handle_exit - called right after the IPI handler + * @ipinr: the IPI number + * + * The @ipinr value must be valid and the action name associated with + * the IPI value is given in the trace. + */ +DEFINE_EVENT_CONDITION(ipi, ipi_handler_exit, + + TP_PROTO(int ipinr), + + TP_ARGS(ipinr), + + TP_CONDITION(ipinr < NR_IPI && ipinr >= 0) +); + +/** + * ipi_raise - called when a smp cross call is made + * @ipinr: the IPI number + * @cpumask: the recipients for the IPI + * + * The @ipinr value must be valid and the action name associated with + * the IPI value is given in the trace as well as the cpumask of the + * targeted cpus. + */ +TRACE_EVENT_CONDITION(ipi_raise, + + TP_PROTO(const struct cpumask *cpumask, int ipinr), + + TP_ARGS(cpumask, ipinr), + + TP_CONDITION(ipinr < NR_IPI && ipinr >= 0), + + TP_STRUCT__entry( + __field(int, ipinr) + __field(const struct cpumask *, cpumask) + __dynamic_array(char, buf, NR_CPUS) + ), + + TP_fast_assign( + __entry->ipinr = ipinr; + __entry->cpumask = cpumask; + ), + + TP_printk("ipi=%d, cpumask=0x%s, name=%s", __entry->ipinr, + show_cpumask(__entry->cpumask), + show_ipi_name(__entry->ipinr)) +); + +#endif /* _TRACE_IPI_H */ + +/* This part must be outside protection */ +#include