From patchwork Wed Nov 6 08:25:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime COQUELIN X-Patchwork-Id: 21350 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yh0-f72.google.com (mail-yh0-f72.google.com [209.85.213.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 8EDE725E6D for ; Wed, 6 Nov 2013 08:27:30 +0000 (UTC) Received: by mail-yh0-f72.google.com with SMTP id z20sf8958691yhz.7 for ; Wed, 06 Nov 2013 00:27:30 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=KEvTSuJWLxRQQkjjKeDpmzCHRkcRczXreC7EnlAr9FM=; b=QP30v4GsuFnAYp1pUaNVPVnq5UNIJP4NOFDj2mSC/zqD7Fot8pvVtp80m9pGdIG2hf g10ztCOy4cVuNi+qxnrJ4tWQN02KsuCQEVMEGfTZqQmH5xv6H1bGgbGo9IUgQOaeh7hc HtRf/4CidhrvBXC/hoonXE9d1Zmba1G6kFkRE96Kkp0FjAZ4UWR4lBqBNEu5epkA7mjT OJ0ucg/q6rGO3D8ifMCUJdf79IrQNq1+ydzGtPlfUIA7QR4bObE+Kn5pLm1oPYVxcs6U jPpXExL8ZvRZTG/FUIiLgR4yCLa+dGYMRm3qZuIY9NbET1tYMWAJs65Y91457J8RFeRB aC9A== X-Gm-Message-State: ALoCoQnHK9kSs3+zqEotJbl/v/xZT8yFUo5Xq7+75vX87H+AsoqqGmpCrny36LFpQoBiG+geOMu2 X-Received: by 10.52.248.195 with SMTP id yo3mr1348607vdc.1.1383726450377; Wed, 06 Nov 2013 00:27:30 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.120.199 with SMTP id le7ls577959qeb.91.gmail; Wed, 06 Nov 2013 00:27:30 -0800 (PST) X-Received: by 10.221.64.17 with SMTP id xg17mr1384575vcb.5.1383726450249; Wed, 06 Nov 2013 00:27:30 -0800 (PST) Received: from mail-vb0-f46.google.com (mail-vb0-f46.google.com [209.85.212.46]) by mx.google.com with ESMTPS id bj8si8038413vcb.23.2013.11.06.00.27.30 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 06 Nov 2013 00:27:30 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.46 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.46; Received: by mail-vb0-f46.google.com with SMTP id 10so3170195vbe.33 for ; Wed, 06 Nov 2013 00:27:30 -0800 (PST) X-Received: by 10.221.21.133 with SMTP id qs5mr1406719vcb.28.1383726450179; Wed, 06 Nov 2013 00:27:30 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp267380vcz; Wed, 6 Nov 2013 00:27:29 -0800 (PST) X-Received: by 10.14.2.200 with SMTP id 48mr1783232eef.88.1383726449276; Wed, 06 Nov 2013 00:27:29 -0800 (PST) Received: from eu1sys200aog107.obsmtp.com (eu1sys200aog107.obsmtp.com [207.126.144.123]) by mx.google.com with SMTP id z7si17369677eey.116.2013.11.06.00.27.00 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 06 Nov 2013 00:27:29 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.123 is neither permitted nor denied by best guess record for domain of maxime.coquelin@st.com) client-ip=207.126.144.123; Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob107.postini.com ([207.126.147.11]) with SMTP ID DSNKUnn9SDG1nKIfv6ZEqLCf5XYpo5Q+ylic@postini.com; Wed, 06 Nov 2013 08:27:29 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 55FA2DD; Wed, 6 Nov 2013 08:25:14 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 804B24C91; Wed, 6 Nov 2013 08:12:22 +0000 (GMT) Received: from lmenx29l.lme.st.com ([10.201.19.60]) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BQV08834 (AUTH lme00137); Wed, 6 Nov 2013 09:25:41 +0100 From: Maxime COQUELIN To: Wolfram Sang , srinivas.kandagatla@st.com, Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Russell King , Grant Likely , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org Cc: stephen.gallimore@st.com, stuart.menefy@st.com, Lee Jones , gabriel.fernandez@st.com Subject: [PATCH v6 3/4] ARM: STi: Supply I2C configuration to STiH415 SoC Date: Wed, 6 Nov 2013 09:25:14 +0100 Message-Id: <1383726315-27534-4-git-send-email-maxime.coquelin@st.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1383726315-27534-1-git-send-email-maxime.coquelin@st.com> References: <1383726315-27534-1-git-send-email-maxime.coquelin@st.com> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: maxime.coquelin@st.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.46 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch supplies I2C configuration to STiH415 SoC. Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih415-pinctrl.dtsi | 36 ++++++++++++++++++++++ arch/arm/boot/dts/stih415.dtsi | 53 ++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 1d322b2..e56449d 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -86,6 +86,24 @@ }; }; }; + + sbc_i2c0 { + pinctrl_sbc_i2c0_default: sbc_i2c0-default { + st,pins { + sda = <&PIO4 6 ALT1 BIDIR>; + scl = <&PIO4 5 ALT1 BIDIR>; + }; + }; + }; + + sbc_i2c1 { + pinctrl_sbc_i2c1_default: sbc_i2c1-default { + st,pins { + sda = <&PIO3 2 ALT2 BIDIR>; + scl = <&PIO3 1 ALT2 BIDIR>; + }; + }; + }; }; pin-controller-front { @@ -143,6 +161,24 @@ reg = <0x7000 0x100>; st,bank-name = "PIO12"; }; + + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&PIO9 3 ALT1 BIDIR>; + scl = <&PIO9 2 ALT1 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&PIO12 1 ALT1 BIDIR>; + scl = <&PIO12 0 ALT1 BIDIR>; + }; + }; + }; }; pin-controller-rear { diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index 74ab8de..d9c7dd1 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -9,6 +9,7 @@ #include "stih41x.dtsi" #include "stih415-clock.dtsi" #include "stih415-pinctrl.dtsi" +#include / { L2: cache-controller { @@ -83,5 +84,57 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; }; + + i2c@fed40000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfed40000 0x110>; + interrupts = ; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + status = "disabled"; + }; + + i2c@fed41000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfed41000 0x110>; + interrupts = ; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + + status = "disabled"; + }; + + i2c@fe540000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfe540000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c0_default>; + + status = "disabled"; + }; + + i2c@fe541000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfe541000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c1_default>; + + status = "disabled"; + }; }; };