From patchwork Tue Oct 8 16:42:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime COQUELIN X-Patchwork-Id: 20901 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qc0-f199.google.com (mail-qc0-f199.google.com [209.85.216.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 34E2E24697 for ; Tue, 8 Oct 2013 16:44:27 +0000 (UTC) Received: by mail-qc0-f199.google.com with SMTP id u18sf16964116qcx.10 for ; Tue, 08 Oct 2013 09:44:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=Tn05ub7CKcFDNHRBWXy8+lCwQ8vc0PRr06nqEZ0oCZU=; b=biuLqhXSD2WvK8jNUTvsa9B8dg9ylsFy99UjrOqToO4nOs8ve4F6JQR+mvm/kFu6kg 0QkmZJKYQUBrFdXGfVP1HrNhv2ac8lTuy+oNnT6OS3w8EyuOsKKRujbeSqjS8lS+3mXt aHOPZd77LlkQH2guJ52gnW7yLOconbjF+W2w05vCxMCJpsjiegpqoiR3A7oboQremyig QSBeQqrLsQ3/WrjiU5G+nUBq2CHJa+GdwsO6lqP3uJP4Y86mIJ4uadRo7PWtLacYo3TW tBE/Vg3kzW+0dMC4S0/T6EwD7Icxp9jvqM7gIRmBo+ed/QWuw+otKzx63PgSDlqQtzQS q39w== X-Received: by 10.236.117.136 with SMTP id j8mr2291312yhh.18.1381250666680; Tue, 08 Oct 2013 09:44:26 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.29.229 with SMTP id n5ls300277qeh.73.gmail; Tue, 08 Oct 2013 09:44:26 -0700 (PDT) X-Received: by 10.220.91.16 with SMTP id k16mr1725777vcm.21.1381250666567; Tue, 08 Oct 2013 09:44:26 -0700 (PDT) Received: from mail-vb0-f47.google.com (mail-vb0-f47.google.com [209.85.212.47]) by mx.google.com with ESMTPS id tj1si9839431vdc.27.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 08 Oct 2013 09:44:26 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.47 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.47; Received: by mail-vb0-f47.google.com with SMTP id h10so4286641vbh.20 for ; Tue, 08 Oct 2013 09:44:26 -0700 (PDT) X-Gm-Message-State: ALoCoQmaHNVZEJQQLwQf2V1GC5uohvQwrOy5X58HBhdU6LPdkn1nOSdAROlNVjXdsATsGG1omGfO X-Received: by 10.52.34.109 with SMTP id y13mr1483058vdi.8.1381250666386; Tue, 08 Oct 2013 09:44:26 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp219439vcz; Tue, 8 Oct 2013 09:44:25 -0700 (PDT) X-Received: by 10.14.219.198 with SMTP id m46mr3659032eep.41.1381250664114; Tue, 08 Oct 2013 09:44:24 -0700 (PDT) Received: from eu1sys200aog119.obsmtp.com (eu1sys200aog119.obsmtp.com [207.126.144.147]) by mx.google.com with SMTP id t9si28505297eeo.35.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 08 Oct 2013 09:44:24 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.147 is neither permitted nor denied by best guess record for domain of maxime.coquelin@st.com) client-ip=207.126.144.147; Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob119.postini.com ([207.126.147.11]) with SMTP ID DSNKUlQ2Qag170OpycNwQjSARDGTGodwTonN@postini.com; Tue, 08 Oct 2013 16:44:23 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B961C12F; Tue, 8 Oct 2013 16:42:47 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 18A162A91; Tue, 8 Oct 2013 16:29:59 +0000 (GMT) Received: from lmenx29l.bri.st.com (lmenx29l.bri.st.com [10.65.5.31]) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BOG28658 (AUTH lme00137); Tue, 8 Oct 2013 18:43:07 +0200 From: Maxime COQUELIN To: Wolfram Sang , srinivas.kandagatla@st.com, Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Russell King , Grant Likely , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org Cc: stephen.gallimore@st.com, stuart.menefy@st.com, Lee Jones , gabriel.fernandez@st.com, Maxime Coquelin Subject: [PATCH v4 3/4] ARM: STi: Supply I2C configuration to STiH415 SoC Date: Tue, 8 Oct 2013 18:42:55 +0200 Message-Id: <1381250576-7916-4-git-send-email-maxime.coquelin@st.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1381250576-7916-1-git-send-email-maxime.coquelin@st.com> References: <1381250576-7916-1-git-send-email-maxime.coquelin@st.com> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: maxime.coquelin@st.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.47 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch supplies I2C configuration to STiH415 SoC. Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih415-pinctrl.dtsi | 36 ++++++++++++++++++++++ arch/arm/boot/dts/stih415.dtsi | 53 ++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 1d322b2..e56449d 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -86,6 +86,24 @@ }; }; }; + + sbc_i2c0 { + pinctrl_sbc_i2c0_default: sbc_i2c0-default { + st,pins { + sda = <&PIO4 6 ALT1 BIDIR>; + scl = <&PIO4 5 ALT1 BIDIR>; + }; + }; + }; + + sbc_i2c1 { + pinctrl_sbc_i2c1_default: sbc_i2c1-default { + st,pins { + sda = <&PIO3 2 ALT2 BIDIR>; + scl = <&PIO3 1 ALT2 BIDIR>; + }; + }; + }; }; pin-controller-front { @@ -143,6 +161,24 @@ reg = <0x7000 0x100>; st,bank-name = "PIO12"; }; + + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&PIO9 3 ALT1 BIDIR>; + scl = <&PIO9 2 ALT1 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&PIO12 1 ALT1 BIDIR>; + scl = <&PIO12 0 ALT1 BIDIR>; + }; + }; + }; }; pin-controller-rear { diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index 74ab8de..eb4fccb 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -9,6 +9,7 @@ #include "stih41x.dtsi" #include "stih415-clock.dtsi" #include "stih415-pinctrl.dtsi" +#include / { L2: cache-controller { @@ -83,5 +84,57 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; }; + + i2c@fed40000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfed40000 0x110>; + interrupts = ; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + status = "disabled"; + }; + + i2c@fed41000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfed41000 0x110>; + interrupts = ; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + + status = "disabled"; + }; + + i2c@fe540000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfe540000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c0_default>; + + status = "disabled"; + }; + + i2c@fe541000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfe541000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c1_default>; + + status = "disabled"; + }; }; };