From patchwork Tue Oct 8 16:42:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime COQUELIN X-Patchwork-Id: 20904 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-gg0-f200.google.com (mail-gg0-f200.google.com [209.85.161.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1E41824697 for ; Tue, 8 Oct 2013 16:44:32 +0000 (UTC) Received: by mail-gg0-f200.google.com with SMTP id n5sf11017390ggj.7 for ; Tue, 08 Oct 2013 09:44:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=QHg55W/ct0EdVwiCftXy0CxwBtS2117jxdHLFj+YX3M=; b=CIkAzfoJFvCYWqjHk0Y3smzd+X+3D/4OlFvGKRHYkQRA83homN+6hi2ctUfIte7w/0 idDPqZ7Bcp4XVENQURQsAvIKIywtsCR2yo9xn3hbttFekTKpyoJIJ2bJDp23VOko/cqF fEHuby74oLm1owWGEYF/rRNwKFUAEw9XI5aKm6UkDGLMw1s3VZ8fpCX8bQ5UxAfCt0Z8 kd7KI5K8zkEG/Cu3fbTG031FaF0uDxgwduU60lws1VhgHBJtUmf2gijCXCUmjd2g6MJQ g4ve5I2iRvwF+RUxP1dZ+JAoX7rXZV/2GgbU9JwqbSqtjU/c9i53A1gJ7vYK/shly8mE 8F/g== X-Received: by 10.236.14.100 with SMTP id c64mr2577090yhc.38.1381250671875; Tue, 08 Oct 2013 09:44:31 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.5.9 with SMTP id o9ls302342qeo.49.gmail; Tue, 08 Oct 2013 09:44:31 -0700 (PDT) X-Received: by 10.52.35.136 with SMTP id h8mr1422796vdj.6.1381250671798; Tue, 08 Oct 2013 09:44:31 -0700 (PDT) Received: from mail-vb0-f44.google.com (mail-vb0-f44.google.com [209.85.212.44]) by mx.google.com with ESMTPS id ug9si9850276vcb.107.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 08 Oct 2013 09:44:31 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.44 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.44; Received: by mail-vb0-f44.google.com with SMTP id e13so4531590vbg.31 for ; Tue, 08 Oct 2013 09:44:31 -0700 (PDT) X-Gm-Message-State: ALoCoQm494THiOYPsm7uDl4OFhzYaJq2AI8OSpto53ZkD8c+/uNVNiHRUjrpVwxstiA0hMG5f6K5 X-Received: by 10.52.32.37 with SMTP id f5mr1419265vdi.17.1381250671687; Tue, 08 Oct 2013 09:44:31 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp219451vcz; Tue, 8 Oct 2013 09:44:30 -0700 (PDT) X-Received: by 10.14.103.69 with SMTP id e45mr3686916eeg.51.1381250664173; Tue, 08 Oct 2013 09:44:24 -0700 (PDT) Received: from eu1sys200aog114.obsmtp.com (eu1sys200aog114.obsmtp.com [207.126.144.137]) by mx.google.com with SMTP id l4si28481197eew.131.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 08 Oct 2013 09:44:24 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.137 is neither permitted nor denied by best guess record for domain of maxime.coquelin@st.com) client-ip=207.126.144.137; Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob114.postini.com ([207.126.147.11]) with SMTP ID DSNKUlQ2Qag170OpycNwQjSARDGTGodwTonN@postini.com; Tue, 08 Oct 2013 16:44:24 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 52A68153; Tue, 8 Oct 2013 16:42:46 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A44C62A90; Tue, 8 Oct 2013 16:29:57 +0000 (GMT) Received: from lmenx29l.bri.st.com (lmenx29l.bri.st.com [10.65.5.31]) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BOG28653 (AUTH lme00137); Tue, 8 Oct 2013 18:43:06 +0200 From: Maxime COQUELIN To: Wolfram Sang , srinivas.kandagatla@st.com, Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Russell King , Grant Likely , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org Cc: stephen.gallimore@st.com, stuart.menefy@st.com, Lee Jones , gabriel.fernandez@st.com, Maxime Coquelin Subject: [PATCH v4 2/4] ARM: STi: Supply I2C configuration to STiH416 SoC Date: Tue, 8 Oct 2013 18:42:54 +0200 Message-Id: <1381250576-7916-3-git-send-email-maxime.coquelin@st.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1381250576-7916-1-git-send-email-maxime.coquelin@st.com> References: <1381250576-7916-1-git-send-email-maxime.coquelin@st.com> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: maxime.coquelin@st.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.44 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch supplies I2C configuration to STiH416 SoC. Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416-pinctrl.dtsi | 35 +++++++++++++++++++++ arch/arm/boot/dts/stih416.dtsi | 53 ++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index 0f246c9..b29ff4b 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -97,6 +97,24 @@ }; }; }; + + sbc_i2c0 { + pinctrl_sbc_i2c0_default: sbc_i2c0-default { + st,pins { + sda = <&PIO4 6 ALT1 BIDIR>; + scl = <&PIO4 5 ALT1 BIDIR>; + }; + }; + }; + + sbc_i2c1 { + pinctrl_sbc_i2c1_default: sbc_i2c1-default { + st,pins { + sda = <&PIO3 2 ALT2 BIDIR>; + scl = <&PIO3 1 ALT2 BIDIR>; + }; + }; + }; }; pin-controller-front { @@ -175,6 +193,23 @@ }; }; + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&PIO9 3 ALT1 BIDIR>; + scl = <&PIO9 2 ALT1 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&PIO12 1 ALT1 BIDIR>; + scl = <&PIO12 0 ALT1 BIDIR>; + }; + }; + }; }; pin-controller-rear { diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 1a0326e..e8eb251 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -9,6 +9,7 @@ #include "stih41x.dtsi" #include "stih416-clock.dtsi" #include "stih416-pinctrl.dtsi" +#include / { L2: cache-controller { compatible = "arm,pl310-cache"; @@ -92,5 +93,57 @@ pinctrl-0 = <&pinctrl_sbc_serial1>; clocks = <&CLK_SYSIN>; }; + + i2c@fed40000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfed40000 0x110>; + interrupts = ; + clocks = <&CLK_S_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + status = "disabled"; + }; + + i2c@fed41000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfed41000 0x110>; + interrupts = ; + clocks = <&CLK_S_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + + status = "disabled"; + }; + + i2c@fe540000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfe540000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c0_default>; + + status = "disabled"; + }; + + i2c@fe541000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfe541000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c1_default>; + + status = "disabled"; + }; }; };