From patchwork Fri Oct 4 13:25:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 20827 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f71.google.com (mail-qa0-f71.google.com [209.85.216.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 4F70A25E85 for ; Fri, 4 Oct 2013 13:25:18 +0000 (UTC) Received: by mail-qa0-f71.google.com with SMTP id k15sf2641366qaq.6 for ; Fri, 04 Oct 2013 06:25:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=BwwpmNlLI7QOSfj/kjmAnDkNlGh9ixTtwFCHmnA1Oek=; b=KmWYLMCOdWAhQmFgURN4eNgJTwP21q9MH4a/6DGkGcpJ1NvJrOpMlesad7h9FFpWFb 8LsQ/JG5jpEOHXj7VCXb9AwbjYYwJWBjSFb3znytyfbnZ14S2eUiHZUZLjoLdjvhUruL mKeV4x5vQUqgra7jIWpJqiKLXOlCo/CMQP82v36l44ErbNFeCXFIoUv7A9/DMlc51M2j 1zBUfvLcdKifUAVGv1RtwOY0GtcVkA5VLfLYLsWyOrQ3ODlDWygSMmusgfzIJuVKDZT5 VrAMVzIFO6uVzhSkEG8qQzUhPlxahbHVep3T4UkJvxMcCxdXVxFX19ywOxB0SGF+/TIk FpCQ== X-Received: by 10.236.0.232 with SMTP id 68mr11880610yhb.16.1380893117645; Fri, 04 Oct 2013 06:25:17 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.99.106 with SMTP id ep10ls1430487qeb.59.gmail; Fri, 04 Oct 2013 06:25:17 -0700 (PDT) X-Received: by 10.221.6.195 with SMTP id ol3mr80681vcb.34.1380893117481; Fri, 04 Oct 2013 06:25:17 -0700 (PDT) Received: from mail-ve0-f173.google.com (mail-ve0-f173.google.com [209.85.128.173]) by mx.google.com with ESMTPS id fx4si3302009vdc.104.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 04 Oct 2013 06:25:17 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.173; Received: by mail-ve0-f173.google.com with SMTP id cz12so2405570veb.4 for ; Fri, 04 Oct 2013 06:25:17 -0700 (PDT) X-Gm-Message-State: ALoCoQlWpHq/Byj82ewqxjdsyCqKDT3ttUo3AVL+++9g3QooZVZZY/I5KZfYPonxWDI9CRWYB3bQ X-Received: by 10.58.100.144 with SMTP id ey16mr257035veb.25.1380893117155; Fri, 04 Oct 2013 06:25:17 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp40043vcz; Fri, 4 Oct 2013 06:25:16 -0700 (PDT) X-Received: by 10.15.23.69 with SMTP id g45mr2011650eeu.90.1380893115576; Fri, 04 Oct 2013 06:25:15 -0700 (PDT) Received: from mail-ea0-f170.google.com (mail-ea0-f170.google.com [209.85.215.170]) by mx.google.com with ESMTPS id b1si10531308eep.167.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 04 Oct 2013 06:25:15 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.215.170 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=209.85.215.170; Received: by mail-ea0-f170.google.com with SMTP id h14so1807584eak.15 for ; Fri, 04 Oct 2013 06:25:14 -0700 (PDT) X-Received: by 10.15.83.2 with SMTP id b2mr21998231eez.28.1380893114834; Fri, 04 Oct 2013 06:25:14 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id j7sm28056976eeo.15.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 04 Oct 2013 06:25:13 -0700 (PDT) From: Linus Walleij To: Thomas Gleixner , linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, Linus Walleij Subject: [PATCH] irqchip: versatile FPGA: support cascaded interrupts from DT Date: Fri, 4 Oct 2013 15:25:06 +0200 Message-Id: <1380893106-7550-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The Versatile FPGA interrupt controller supports cascading interrupts, i.e. that its output is connected to the input of another interrupt controller. This makes it possible to pass a parent interrupt from the device tree and print it in the boot log if applicable. Cc: Thomas Gleixner Signed-off-by: Linus Walleij --- TGLX: I can take this through ARM SoC if you're happy with it and prefer it that way, but it merges just as fine as it is on the IRQ tree. --- .../devicetree/bindings/arm/versatile-fpga-irq.txt | 5 +++++ drivers/irqchip/irq-versatile-fpga.c | 15 +++++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt index 9989eda..c9cf605 100644 --- a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt +++ b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt @@ -29,3 +29,8 @@ pic: pic@14000000 { clear-mask = <0xffffffff>; valid-mask = <0x003fffff>; }; + +Optional properties: +- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ + output is simply connected to the input of another IRQ controller, + then the parent IRQ shall be specified in this property. diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c index 47a52ab..3ae2bb8 100644 --- a/drivers/irqchip/irq-versatile-fpga.c +++ b/drivers/irqchip/irq-versatile-fpga.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -167,8 +168,12 @@ void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start, f->used_irqs++; } - pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n", + pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs", fpga_irq_id, name, base, f->used_irqs); + if (parent_irq != -1) + pr_cont(", parent IRQ: %d\n", parent_irq); + else + pr_cont("\n"); fpga_irq_id++; } @@ -180,6 +185,7 @@ int __init fpga_irq_of_init(struct device_node *node, void __iomem *base; u32 clear_mask; u32 valid_mask; + int parent_irq; if (WARN_ON(!node)) return -ENODEV; @@ -193,7 +199,12 @@ int __init fpga_irq_of_init(struct device_node *node, if (of_property_read_u32(node, "valid-mask", &valid_mask)) valid_mask = 0; - fpga_irq_init(base, node->name, 0, -1, valid_mask, node); + /* Some chips are cascaded from a parent IRQ */ + parent_irq = irq_of_parse_and_map(node, 0); + if (!parent_irq) + parent_irq = -1; + + fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node); writel(clear_mask, base + IRQ_ENABLE_CLEAR); writel(clear_mask, base + FIQ_ENABLE_CLEAR);