From patchwork Wed Sep 18 10:01:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime COQUELIN X-Patchwork-Id: 20384 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qc0-f200.google.com (mail-qc0-f200.google.com [209.85.216.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 5E9E8246E9 for ; Wed, 18 Sep 2013 10:03:13 +0000 (UTC) Received: by mail-qc0-f200.google.com with SMTP id x20sf6976728qcv.7 for ; Wed, 18 Sep 2013 03:03:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=J3hJ06zSlZGVazEq4Wwwez6WqoH+lWSmLX4iB9wl0KI=; b=f6Zq0gYe0wO7kNNO9OmcHE+uSI9a3nyCRt3Oo6gVtWRjkLO1DGUKNt7yrdZPMRWKrj SBhNslvGhQ135dRucVbQxqilT4i/+npBLguBum2RhHr0PXOH3Gq9ScMAOHtDs5NuvN10 7N1A0rf5fU4YSDg5ySfMHt1NhNgsqdiYxOtFf0pZhjPzizY18IqB0Zp1bObz3MILSEia g5MGspOZQkdkh40iawyPGGnPnMfrW4d0jXUPtVLk4gcPgNF4fYpJQD/fjpPg4gH+iYVg rDJZdb1+O4cz+3HgW4pBNX6EDWsRlc5g9gKHEqJGg3fS92rRq63tFqyeIEFJEVE1S3xI NouQ== X-Gm-Message-State: ALoCoQkU/Mqamyly8SksupYSJRG/zp6zKrGqdK4O1A1FasWogQo/MDh4yHBMRNRUy60y+RdU9oyr X-Received: by 10.236.52.7 with SMTP id d7mr5888102yhc.32.1379498592745; Wed, 18 Sep 2013 03:03:12 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.94.8 with SMTP id cy8ls3147835qeb.18.gmail; Wed, 18 Sep 2013 03:03:12 -0700 (PDT) X-Received: by 10.220.145.132 with SMTP id d4mr37028605vcv.9.1379498592596; Wed, 18 Sep 2013 03:03:12 -0700 (PDT) Received: from mail-vc0-f176.google.com (mail-vc0-f176.google.com [209.85.220.176]) by mx.google.com with ESMTPS id zw10si273366vdb.70.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 18 Sep 2013 03:03:12 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.176; Received: by mail-vc0-f176.google.com with SMTP id lf11so4984691vcb.7 for ; Wed, 18 Sep 2013 03:03:12 -0700 (PDT) X-Received: by 10.52.113.99 with SMTP id ix3mr13183037vdb.22.1379498592504; Wed, 18 Sep 2013 03:03:12 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp209013vcz; Wed, 18 Sep 2013 03:03:11 -0700 (PDT) X-Received: by 10.14.127.137 with SMTP id d9mr342213eei.90.1379498590457; Wed, 18 Sep 2013 03:03:10 -0700 (PDT) Received: from eu1sys200aog106.obsmtp.com (eu1sys200aog106.obsmtp.com [207.126.144.121]) by mx.google.com with SMTP id x49si897432een.264.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 18 Sep 2013 03:03:10 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.121 is neither permitted nor denied by best guess record for domain of maxime.coquelin@st.com) client-ip=207.126.144.121; Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob106.postini.com ([207.126.147.11]) with SMTP ID DSNKUjl6Na565srPkAPLbo4cOGqLuM1jmpVW@postini.com; Wed, 18 Sep 2013 10:03:10 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A4F69D3; Wed, 18 Sep 2013 10:01:40 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 57A974CFC; Wed, 18 Sep 2013 09:48:54 +0000 (GMT) Received: from lmenx29l.lme.st.com (lmenx29l.lme.st.com [10.201.23.80] (may be forged)) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BMK69475 (AUTH lme00137); Wed, 18 Sep 2013 12:01:55 +0200 From: Maxime COQUELIN To: Wolfram Sang , srinivas.kandagatla@st.com, Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Russell King , Grant Likely , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org Cc: stephen.gallimore@st.com, stuart.menefy@st.com, Lee Jones , gabriel.fernandez@st.com, olivier.clergeaud@st.com, Maxime Coquelin Subject: [PATCH 2/4] ARM: STi: Supply I2C configuration to STiH416 SoC Date: Wed, 18 Sep 2013 12:01:21 +0200 Message-Id: <1379498483-4236-3-git-send-email-maxime.coquelin@st.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1379498483-4236-1-git-send-email-maxime.coquelin@st.com> References: <1379498483-4236-1-git-send-email-maxime.coquelin@st.com> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: maxime.coquelin@st.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch supplies I2C configuration to STiH416 SoC. Cc: Srinivas Kandagatla Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416-pinctrl.dtsi | 35 ++++++++++++++++++++ arch/arm/boot/dts/stih416.dtsi | 57 ++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+) diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index 0f246c9..b29ff4b 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -97,6 +97,24 @@ }; }; }; + + sbc_i2c0 { + pinctrl_sbc_i2c0_default: sbc_i2c0-default { + st,pins { + sda = <&PIO4 6 ALT1 BIDIR>; + scl = <&PIO4 5 ALT1 BIDIR>; + }; + }; + }; + + sbc_i2c1 { + pinctrl_sbc_i2c1_default: sbc_i2c1-default { + st,pins { + sda = <&PIO3 2 ALT2 BIDIR>; + scl = <&PIO3 1 ALT2 BIDIR>; + }; + }; + }; }; pin-controller-front { @@ -175,6 +193,23 @@ }; }; + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&PIO9 3 ALT1 BIDIR>; + scl = <&PIO9 2 ALT1 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&PIO12 1 ALT1 BIDIR>; + scl = <&PIO12 0 ALT1 BIDIR>; + }; + }; + }; }; pin-controller-rear { diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 1a0326e..8856470 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -9,6 +9,7 @@ #include "stih41x.dtsi" #include "stih416-clock.dtsi" #include "stih416-pinctrl.dtsi" +#include / { L2: cache-controller { compatible = "arm,pl310-cache"; @@ -92,5 +93,61 @@ pinctrl-0 = <&pinctrl_sbc_serial1>; clocks = <&CLK_SYSIN>; }; + + i2c0: i2c@fed40000{ + compatible = "st,comms-i2c"; + status = "disabled"; + reg = <0xfed40000 0x110>; + interrupts = ; + clocks = <&CLK_S_ICN_REG_0>; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + st,glitches; + st,glitch-clk = <500>; + st,glitch-dat = <500>; + }; + + i2c1: i2c@fed41000{ + compatible = "st,comms-i2c"; + status = "disabled"; + reg = <0xfed41000 0x110>; + interrupts = ; + clocks = <&CLK_S_ICN_REG_0>; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + st,glitches; + st,glitch-clk = <500>; + st,glitch-dat = <500>; + }; + + sbc_i2c0: i2c@fe540000{ + compatible = "st,comms-i2c"; + status = "disabled"; + reg = <0xfe540000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c0_default>; + st,glitches; + st,glitch-clk = <500>; + st,glitch-dat = <500>; + }; + + sbc_i2c1: i2c@fe541000{ + compatible = "st,comms-i2c"; + status = "disabled"; + reg = <0xfe541000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c1_default>; + st,glitches; + st,glitch-clk = <500>; + st,glitch-dat = <500>; + }; }; };