From patchwork Mon Sep 16 09:17:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean Pihet X-Patchwork-Id: 20320 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f72.google.com (mail-qa0-f72.google.com [209.85.216.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 6A815248D3 for ; Mon, 16 Sep 2013 09:17:49 +0000 (UTC) Received: by mail-qa0-f72.google.com with SMTP id j7sf1741481qaq.11 for ; Mon, 16 Sep 2013 02:17:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=Xsqhd2ZDndYEED1966zsGv8KF0uRZz8RCGoAQeBcavg=; b=R5ZHcUFNyIl1MvX30K5KfBheNNIwbqtb0qRD+SQuECyFNLdrQsMtNW5BR5jUn7T2YO VDRpP6uk9nP31q/91qIrdthc793aGv5/YCiUIiBKCQtyHYRNJ7pnRNu3WVbCmXHG9sOt yGUeP9Onz3OA7/qpxdrFYr2KTvEhxzvqobG4AtFnC6hzAxtdCVZiR06plAyjESxw1szw KeCpGBpeShmZtlCxrlhbLWIDMRMwgb/KoCwt+SyLt2Ru0zuNRHaJ5WWwYDWLuKxaidbv aeXtEom2o6NcyfzPokf0M2AkC/vs2MPMfPUX5VRFPLcIspBBqtv5muPATb80q9N5wMIx ZA+w== X-Gm-Message-State: ALoCoQlrPYu12YmNgkIMx3VJmw0MN/xM1yS3+z3L0PJsk0kMC9AmUPFnBDNhFiCBTqVCgzHQXrZk X-Received: by 10.236.32.74 with SMTP id n50mr10223164yha.13.1379323069131; Mon, 16 Sep 2013 02:17:49 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.76.100 with SMTP id j4ls2182338qew.29.gmail; Mon, 16 Sep 2013 02:17:49 -0700 (PDT) X-Received: by 10.52.108.230 with SMTP id hn6mr399494vdb.28.1379323069043; Mon, 16 Sep 2013 02:17:49 -0700 (PDT) Received: from mail-ve0-f173.google.com (mail-ve0-f173.google.com [209.85.128.173]) by mx.google.com with ESMTPS id b5si6880704vel.24.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 16 Sep 2013 02:17:49 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.173; Received: by mail-ve0-f173.google.com with SMTP id cz12so2667369veb.4 for ; Mon, 16 Sep 2013 02:17:49 -0700 (PDT) X-Received: by 10.58.161.116 with SMTP id xr20mr25873867veb.2.1379323068932; Mon, 16 Sep 2013 02:17:48 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp85947vcz; Mon, 16 Sep 2013 02:17:48 -0700 (PDT) X-Received: by 10.14.213.68 with SMTP id z44mr795722eeo.70.1379323067758; Mon, 16 Sep 2013 02:17:47 -0700 (PDT) Received: from mail-ee0-f51.google.com (mail-ee0-f51.google.com [74.125.83.51]) by mx.google.com with ESMTPS id 7si15127621eeo.49.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 16 Sep 2013 02:17:47 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.83.51 is neither permitted nor denied by best guess record for domain of jean.pihet@linaro.org) client-ip=74.125.83.51; Received: by mail-ee0-f51.google.com with SMTP id c1so1880112eek.10 for ; Mon, 16 Sep 2013 02:17:47 -0700 (PDT) X-Received: by 10.15.76.135 with SMTP id n7mr1962298eey.60.1379323067156; Mon, 16 Sep 2013 02:17:47 -0700 (PDT) Received: from localhost.localdomain (45.104-241-81.adsl-dyn.isp.belgacom.be. [81.241.104.45]) by mx.google.com with ESMTPSA id f49sm40208333eec.7.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 16 Sep 2013 02:17:46 -0700 (PDT) From: Jean Pihet To: Will Deacon , Jiri Olsa , linux-kernel@vger.kernel.org, linaro-kernel@lists.linaro.org, linux-arm-kernel@lists.infradead.org, Ingo Molnar Cc: patches@linaro.org, Jean Pihet Subject: [PATCH 1/4] ARM: perf: add support for perf registers API Date: Mon, 16 Sep 2013 11:17:30 +0200 Message-Id: <1379323053-11458-2-git-send-email-jean.pihet@linaro.org> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1379323053-11458-1-git-send-email-jean.pihet@linaro.org> References: <1379323053-11458-1-git-send-email-jean.pihet@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: jean.pihet@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Will Deacon This patch implements the functions required for the perf registers API, allowing the perf tool to interface kernel register dumps with libunwind in order to provide userspace backtracing. Signed-off-by: Will Deacon Cc: Jean Pihet --- arch/arm/Kconfig | 2 ++ arch/arm/include/uapi/asm/Kbuild | 1 + arch/arm/include/uapi/asm/perf_regs.h | 23 +++++++++++++++++++++++ arch/arm/kernel/Makefile | 1 + arch/arm/kernel/perf_regs.c | 30 ++++++++++++++++++++++++++++++ 5 files changed, 57 insertions(+) create mode 100644 arch/arm/include/uapi/asm/perf_regs.h create mode 100644 arch/arm/kernel/perf_regs.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3f7714d..5595888 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -51,6 +51,8 @@ config ARM select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND select HAVE_OPROFILE if (HAVE_PERF_EVENTS) select HAVE_PERF_EVENTS + select HAVE_PERF_REGS + select HAVE_PERF_USER_STACK_DUMP select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_SYSCALL_TRACEPOINTS select HAVE_UID16 diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild index 18d76fd..70a1c9d 100644 --- a/arch/arm/include/uapi/asm/Kbuild +++ b/arch/arm/include/uapi/asm/Kbuild @@ -7,6 +7,7 @@ header-y += hwcap.h header-y += ioctls.h header-y += kvm_para.h header-y += mman.h +header-y += perf_regs.h header-y += posix_types.h header-y += ptrace.h header-y += setup.h diff --git a/arch/arm/include/uapi/asm/perf_regs.h b/arch/arm/include/uapi/asm/perf_regs.h new file mode 100644 index 0000000..ce59448 --- /dev/null +++ b/arch/arm/include/uapi/asm/perf_regs.h @@ -0,0 +1,23 @@ +#ifndef _ASM_ARM_PERF_REGS_H +#define _ASM_ARM_PERF_REGS_H + +enum perf_event_arm_regs { + PERF_REG_ARM_R0, + PERF_REG_ARM_R1, + PERF_REG_ARM_R2, + PERF_REG_ARM_R3, + PERF_REG_ARM_R4, + PERF_REG_ARM_R5, + PERF_REG_ARM_R6, + PERF_REG_ARM_R7, + PERF_REG_ARM_R8, + PERF_REG_ARM_R9, + PERF_REG_ARM_R10, + PERF_REG_ARM_FP, + PERF_REG_ARM_IP, + PERF_REG_ARM_SP, + PERF_REG_ARM_LR, + PERF_REG_ARM_PC, + PERF_REG_ARM_MAX, +}; +#endif /* _ASM_ARM_PERF_REGS_H */ diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 5140df5f..9b818ca 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o +obj-$(CONFIG_PERF_EVENTS) += perf_regs.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o diff --git a/arch/arm/kernel/perf_regs.c b/arch/arm/kernel/perf_regs.c new file mode 100644 index 0000000..6e4379c --- /dev/null +++ b/arch/arm/kernel/perf_regs.c @@ -0,0 +1,30 @@ + +#include +#include +#include +#include +#include +#include + +u64 perf_reg_value(struct pt_regs *regs, int idx) +{ + if (WARN_ON_ONCE((u32)idx >= PERF_REG_ARM_MAX)) + return 0; + + return regs->uregs[idx]; +} + +#define REG_RESERVED (~((1ULL << PERF_REG_ARM_MAX) - 1)) + +int perf_reg_validate(u64 mask) +{ + if (!mask || mask & REG_RESERVED) + return -EINVAL; + + return 0; +} + +u64 perf_reg_abi(struct task_struct *task) +{ + return PERF_SAMPLE_REGS_ABI_32; +}